Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3419 / 3738

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MMC/SD/SDIO Use Cases and Tips
24.6.1.3.3 MMC Bus Setting Change After Card Identification
After CMD3 command transfer is completed successfully, an auto-negotiation on voltage value an start.
This is the frontier when the MMCHS controller should switch from identification mode to transfer mode.
This impacts the controller in a way that it should change its bus state from open drain to push-pull.
Table 24-21 gives several registers and their values.
Table 24-21. MMC Bus Setting Change Table
Register Name Register Address Value Value Description
MMCHS1. MMCHS_CON 0x4809C02C 0x00000000 Bus is now in push-pull mode.
MMCHS1. MMCHS_HCTL 0x4809C128 0x00000B00 Bus power is on, 1.8V is selected.
MMCHS1. MMCHS_SYSCTL 0x4809C12C 0x00003C07 MMCHS controller's internal clock is stable and
enabled, MMC card's clock is on. Divider value is
240 which means that MMCHS controller is still
supplying a 400 kHz clock.
24.6.1.3.4 Reading the CSD Register of an MMC Card
After settling on a voltage value, additional information must be read from the MMC card. This data is
stored in MMC card CSD register. The card sends CSD register content after receiving CMD9 command.
The CSD register holds important information on the card, MMC system specification version support,
maximum clock speed support, memory capacity, minimum block length, read and write transfer latency
timings.
24.6.1.3.4.1 Sending CMD9
This command asks the card to send its csd register's content (see Table 24-22 ). The 136 bit (128 bits are
valid payload) response is received in MMCHS1. MMCHS_RSP10 , MMCHS1. MMCHS_RSP32 ,
MMCHS1. MMCHS_RSP54 and MMCHS1. MMCHS_RSP76 registers. CMD9 is an addressed command
which means that card's address must be written in MMCHS1. MMCHS_ARG register before the command
is issued.
Table 24-22. Sending CMD9
Register Name Register Address Value Value Description
MMCHS1. MMCHS_CON 0x4809C02C 0x00000000 MMC bus is in push-pull mode.
MMCHS1. MMCHS_IE 0x4809C134 0x00070001 Enables CCRC, CC, CTO and CEB events to occur.
MMCHS1. MMCHS_ISE 0x4809C138 0x00070001 Enables CCRC, CC, CTO and CEB interrupts to
rise.
MMCHS1. MMCHS_CMD 0x4809C10C 0x09090000 Sends CMD9 whose opcode is 9, response type is
136 bits with CCCE enabled.
MMCHS1. MMCHS_ARG 0x4809C108 0x00010000 MMCHS_ARG register carries MMC card's address.
We choose to assign address 1 any other 16 bit
wide value is valid.
After receiving and parsing CMD9 response, MMC card clock speed must change to take advantage to
card's maximum speed. This has an impact on MMC bus as we should perform a clock frequency change.
At this stage the maximum clock frequency will be 20 MHz (see MMC system specification from
www.mmca.org).
Clock frequency change procedure is performed in several steps. See Section 24.5.2.7.2 , MMCHS Clock
Frequency Change.
Table 24-23 shows the value written in MMCHS1. MMCHS_SYSCTL register.
Table 24-23. MMCHS_SYSCTL Value
Register Name Register Address Value Value Description
MMCHS1. MMCHS_SYSCTL 0x4809C12C 0x00000147 MMCHS controller's internal clock is stable and
enabled, MMC card's clock is on. Divider value is 5
which means that MMCHS controller is supplying a
19.2 MHz clock < 20 MHz.
3419 SWPU177N – December 2009 – Revised November 2010 MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated