Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3148 / 3738

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McBSP Basic Programming Model
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If the SRG creates a frame-synchronization signal (FSG) that is derived from an external input clock, the
GSYNC bit determines whether FSG is kept synchronized with pulses on the mcbsp_fsr pin. For more
details, see
Section 21.4.3.3 .
In the digital loopback mode (DLB=1) or analog loopback mode (ALB = 1), the transmit frame
synchronization signal is used as the receive frame synchronization signal. For more details on
frame-sync configuration, see
Section 21.4.3.2 .
21.5.1.6.2.3.2 Set the Transmit Frame-Sync Polarity
McBSPi. MCBSPLP_PCR_REG [3] FSXP bit determines whether frame-synchronization pulses are active
high or active low on the mcbsp_fsx pin.
Transmit frame-synchronization pulses can be generated internally by the SRG or driven by an external
source. The source of frame synchronization is selected by programming the
McBSPi.
MCBSPLP_PCR_REG [11] FSXM bit. FSX is also affected by the
McBSPi. MCBSPLP_SRGR2_REG [12] FSGM bit. For information about the effects of FSXM and FSGM,
see Section 21.5.1.6.2.3.1 ).
When FSR and FSX are inputs (FSXM=FSRM=0, external frame-synchronization pulses), the McBSP
module detects them on the internal falling edge of clock, internal CLKR, and internal CLKX, respectively.
The receive data arriving at the mcbsp_dr pin is also sampled on the falling edge of internal CLKR. These
internal clock signals are either derived from external source via CLK(R/X) pins or driven by the SRG
clock (CLKG) internal to the McBSP module.
When FSR and FSX are outputs, implying that they are driven by the SRG, they are generated (transition
to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data on the mcbsp_dx pin is
output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR_REG) configure the polarities of the
FSR, FSX, CLKR, and CLKX signals, respectively. All FSG (internal FSR, internal FSX) that are internal to
the serial port are active high. If the serial port is configured for external frame synchronization (FSR/FSX
are inputs to McBSP) and FSRP=FSXP=1, the external active-low frame-synchronization signals are
inverted before being sent to the receiver (internal FSR) and transmitter (internal FSX). Similarly, if internal
synchronization (FSR/FSX are output pins and GSYNC=0) is selected and the polarity bit FS(R/X)P=1, the
internal active–high FSG are inverted before being sent to the FS(R/X) pin.
21.5.1.6.2.3.3 Set the SRG Frame-Sync Period and Pulse Width
See Section 21.5.1.5.2.3.3 .
21.5.1.6.2.4 Clock Behavior
21.5.1.6.2.4.1 Set the Transmit Clock Mode
The McBSPi. MCBSPLP_PCR_REG [9] CLKXM bit is used to set the transmit clock mode.
Table 21-33 shows how the CLKXM bit selects the transmit clock and the corresponding status of the
mcbsp_clkx pin. The CLKXP bit determines the polarity of the signal on the mcbsp_clkx pin.
Table 21-33. CLKXM Bit Effect on Transmit Clock and MCBSPLP.CLKX Pin
CLKXM Source of Transmit Clock mcbsp_clkx Pin Status
0 Internal CLKX is driven by an external clock on the Input
mcbsp_clkx pin. CLKX is inverted as determined by
CLKXP before being used.
1 Internal CLKX is driven by the SRG clock, CLKG. Output. CLKG, inverted as determined by CLKXP, is driven
out on mcbsp_clkx.
3148Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated