Texas Instruments OMAP36 Series, Technical Reference Manual

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SCM Functional Description
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Table 13-15. IVA2.2 Boot Modes
IVA2_BOOTMOD[3:0] Value Meaning
0x0 Direct boot: The ROM loader is not executed. Instead, IVA2.2 directly starts executing
the bootstrap at the address contained in the
CONTROL_IVA2_BOOTADDR register.
0x1 Idle boot: The boot loader executes the IDLE instruction.
0x2 Wait in self-loop boot: The boot loader puts IVA2.2 in a self-loop.
0x3 User-defined bootstrap mode: The boot loader copies the boot strap into internal
memory and branches to it.
0x4 The boot loader executes the default context restore code, which is part of the ROM
boot loader.
For further information, see Chapter 5 , IVA2.2 Subsystem.
13.4.7.4 PBIAS LITE Control Register
Table 13-16 describes the CONTROL. CONTROL_PBIAS_LITE register, which controls most of the
settings of the PBIAS0, PBIAS1 cells and their associated extended-drain I/O cells.
Table 13-16. PBIAS Control Register
Physical Address Register Name Description Access
0x4800 2520 CONTROL_PBIAS_LITE Control settings for PBIAS and extended-drain I/O cells R/W
For more information about the PBIAS0 and PBIAS1 cells, see Section 13.4.5 , Extended-Drain I/O Pin
and PBIAS Cells.
13.4.7.5 Temperature Sensor Control Register
Table 13-17 describes the CONTROL. CONTROL_TEMP_SENSOR register, which controls the
temperature sensor.
Table 13-17. Temperature Sensor Register
Physical Address Register Name Description Access
0x4800 2524 CONTROL_TEMP_SENSOR Temperature sensor control register R/W
13.4.7.6 Signal Integrity Parameter Control Registers With Pad Group Assignment
13.4.7.6.1 Signal Integrity Parameter Controls Overview
Most of the I/O cells associated to the device pads are configurable/controllable to deliver their carried
signals to the targeted sink with maximum signal integrity. Configuration of the buffers is done by groups
assignment and not individually per pad. The I/Os parameter control includes : drive strength in terms of
frequency vs. load settings (SDRC) - DS, far-end load settings –LB (GPMC, etc.) , combined slew
rate –SC and load capacitance vs effective transmission line (TL) length – LB controls ( UART3, etc.),
pullup strength (SDMMC) settings, pullup resistance vs capacitance load settings (I2Cx).
The pad group assigned signal integrity controls are provided through the registers described in
Table 13-18 , Signal Integrity Parameter Control Registers.
Table 13-18. Signal Integrity Parameter Control Registers
Physical Address Register Name Description Access
0x4800 2444 CONTROL_PROG_IO0 I/O pad group assignment control register R/W
0x4800 2448 CONTROL_PROG_IO1 I/O pad group assignment control register R/W
0x4800 2408 CONTROL_PROG_IO2 I/O pad group assignment control register R/W
0x4800 2A80 CONTROL_PROG_IO_WKUP1 I/O pad group assignment control register R/W
in the WKUP domain
2476System Control Module SWPU177N – December 2009 – Revised November 2010
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