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L3 Interconnect
Table 9-48. L3_IA_ERROR_LOG_ADDR
Address Offset
0x060
Physical Address
See
to
Description
Error log address register of IA block
Type
R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ADDR
Bits
Field Name
Description
Type
Reset
63:32
Reserved
Reserved
R
0x000000
31:0
ADDR
Address of the command that caused the error
R
0x0000000000
Table 9-49. Register Call Summary for Register L3_IA_ERROR_LOG_ADDR
L3 Interconnect
•
:
•
:
•
9.2.5.2
L3 Target Agent (L3 TA)
This section describes the TA register block. Each TA in L3 interconnect has its own register block.
The following are the TA registers:
•
SDRAM memory scheduler (TA_SMS module)
•
General-purpose memory controller (TA_GPMC module)
•
On-chip memory RAM (TA_OCM_RAM module)
•
On-chip memory ROM (TA_OCM_ROM module)
•
Master D2D (TA_MAD2D module)
•
IVA2.2 subsystem (TA_IVA2.2 module)
•
SGX subsystem (TA_SGX module)
•
L4-Core interconnect (TA_L4_CORE module)
•
L4-Per interconnect (TA_L4_PER module)
•
L4-Emu interconnect (TA_L4_EMU module)
through
lists all initiator target registers and their physical addresses depending on
the module instance.
through
describe the individual common registers in the module instance.
Table 9-50. Target Agent Common Register Summary
Register Name
Type
Register
TA_SMS
TA_GPMC
TA_OCM_RAM
Width
Physical
Physical
Physical
(Bits)
Address
Address
Address
R
64
0x6800 2000
0x6800 2400
0x6800 2800
R
64
0x6800 2018
0x6800 2418
0x6800 2818
RW
64
0x6800 2020
0x6800 2420
0x6800 2820
R
64
0x6800 2028
0x6800 2428
0x6800 2828
RW
64
0x6800 2058
0x6800 2458
0x6800 2858
R
64
0x6800 2060
0x6800 2460
0x6800 2860
2035
SWPU177N – December 2009 – Revised November 2010
Interconnect
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