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Display Subsystem Functional Description
The following example is an output configuration based on the 16-bit interface width and the 24-bit pixel
format (i = 0 or 1) (see also
):
•
The DSS.
[10:9] CYCLEFORMAT bit field is set to 0x3 (three cycles for two pixels).
•
The DSS.
register is set to 0x00000010 (16 bits from pixel 1 for the first cycle).
•
The DSS.
register is set to 0x00080808 (8 bits from pixel 1 and pixel 2 and
alignment of 8 bits from pixel 2 for the second cycle).
•
The DSS.
register is set to 0x00100000 (16 bits from pixel 2 for the third
cycle).
Table 7-36. 16-Bit Interface Configuration/24-Bit Mode
24-Bit Mode
1st Cycle
2nd Cycle
3rd Cycle
Data[15]
R0[7]
B0[7]
G1[7]
Data[14]
R0[6]
B0[6]
G1[6]
Data[13]
R0[5]
B0[5]
G1[5]
Data[12]
R0[4]
B0[4]
G1[4]
Data[11]
R0[3]
B0[3]
G1[3]
Data[10]
R0[2]
B0[2]
G1[2]
Data[9]
R0[1]
B0[1]
G1[1]
Data[8]
R0[0]
B0[0]
G1[0]
Data[7]
G0[7]
R1[7]
B1[7]
Data[6]
G0[6]
R1[6]
B1[6]
Data[5]
G0[5]
R1[5]
B1[5]
Data[4]
G0[4]
R1[4]
B1[4]
Data[3]
G0[3]
R1[3]
B1[3]
Data[2]
G0[2]
R1[2]
B1[2]
Data[1]
G0[1]
R1[1]
B1[1]
Data[0]
G0[0]
R1[0]
B1[0]
7.4.6.5
Unmodified Bits
In a cycle, if every bit in the interface does not have a pixel value, the status of the unused bits can be
programmed to be 0, 1, or the previous value (I/O power consumption optimization).
7.4.6.6
Bypass Mode
In bypass mode, the RFBI path is bypassed and the display controller data and signals are sent directly to
the output interface of the RFBI.
7.4.6.7
Send Commands
The commands are written through the L4 interconnect and into the DSS.
register. After a
command is sent, another one can be accepted by the module and set. If the processing of a command is
not complete, the MPU access to change the command stalls.
7.4.6.8
Read/Write
Depending on the status of A0, WE, and RE, the commands and display/parameter data are written to the
panel (handled by the state-machine for the commands/parameter data and stored in memory for the
display data), or the display data/status values are read from the LCD panel (status and display data in
the LCD panel memory). The polarity of A0 (RFBI_A0 signal), WE (RFBI_WR signal), RE (RFBI_RD
signal), and CSx (RFBI_CSx signal, with x = 0, 1) is programmable.
describes the read/write function.
1689
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated