Public Version
Display Subsystem Functional Description
www.ti.com
Table 7-37. Read/Write Function Description
A0 (RFBI_A0)
WE (RFBI_WR)
RE (RFBI_RD)
Function Description
1
0
1
Display data write, parameter data write
1
1
0
Display data read
0
1
0
Status read
0
0
1
Command data write
A minimum of RFBI_Cs cycle time, as defined in
, is required to keep the RFBI_CSx signal
asserted between write transfers of multiple pixels.
indicates the minimum cycle time for RFBI_CSx, depending on the source of pixels (display
controller or L4 interconnect slave port) and the cycle format (1pixel/cycle, 1 pixel/2 cycles, 1 pixel/3
cycles, or 2 pixels/3 cycles).
Table 7-38. Minimum Cycle Time for CSx/WE Always Asserted
RFBI Performance
[10:9]
Minimum Cycle Time (in Number of L4 Cycles)
CYCLEFORMAT
L4FORMAT
L4 interconnect
1 pixel/cycle
1 pixel
5
1 pixel/2 cycles
1 pixel
4
1 pixel/3 cycles
1 pixel
4
2 pixels/3 cycles
1 pixel
6
1 pixel/cycle
2 pixels
4
1 pixel/2 cycles
2 pixels
4
1 pixel/3 cycles
2 pixels
4
2 pixels/3 cycles
2 pixels
6
Display Controller
1 pixel/cycle
N/A
4
1 pixel/2 cycles
N/A
3
1 pixel/3 cycles
N/A
3
2 pixels/3 cycles
N/A
6
7.4.7 Video Encoder Functionalities
The input formats supported by the encoders are 24-bit 4:4:4 RGB. The encoder output is the DAC stage
(for more information, see
, Display Subsystem Environment). In the display subsystem, the
input format from the display controller is always 24-bit RGB. The RGB-to-YCbCr color space converter
converts the 24-bit RGB pixel data to 24-bit YCbCr data.
The remaining Cb and Cr color components enter the 2-to-1 chrominance decimation, which reduces by
half the chrominance bandwidth and the amount of chrominance data. After the data manager, the
encoder processes in 4:2:2 data path up to the 2x interpolation. A luma delay synchronizes luma to
chrominance data.
shows an overview of the video encoder architecture.
1690
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
