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Camera ISP Basic Programming Model
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Table 6-77. Camera ISP Central-Resource SBL Write-Buffer Overflow Events (continued)
Bit
Event Description
[24] CCDCPRV_2_RSZ_OVF
CCDC/PREVIEW to RESIZER input overflow
This bit is set if the RESIZER input source is sent to
CCDC/PREVIEW engine when the active data (to be resized)
has already showed up at the resizer interface. In such a case,
resizing for this frame cannot take place and the bit is set. This
scenario can happen when a resize of > 4x is required per
frame. Therefore, the RESIZER must operate in two passes. In
the first pass, the input data from CCDC/PREVIEW is directly
resized and written to memory. In the second pass, the resized
data from the first pass is resized again. The next frame from
the CCDC/PREVIEW engine should start only after the second
pass on the previous frame is complete. This bit indicates the
failure status.
[23] CCDC_WBL_OVF
CCDC write-buffer memory overflow
[22] PRV_WBL_OVF
PREVIEW write-buffer memory overflow
[21] RSZ1_WBL_OVF
RESIZER line 1 write-buffer memory overflow
[20] RSZ2_WBL_OVF
RESIZER line 2 write-buffer memory overflow
[19] RSZ3_WBL_OVF
RESIZER line 3 write-buffer memory overflow
[18] RSZ4_WBL_OVF
RESIZER line 4 write-buffer memory overflow
[17] H3A_AF_WBL_OVF
H3A AF write-buffer memory overflow
[16] H3A_AEAWB_WBL_OVF
H3A AE/AWB write-buffer memory overflow
The status of this interrupt can be checked by reading the
register (or
). When the read of the register
occurs (or
), the
register is not automatically reset. To reset the interrupt, a 1 must be written:
•
To the corresponding bit(s) in the
registers
•
To the OVF_IRQ bit in the
register (or
)
Each event that generates an interrupt can be individually mapped to ARM or DSP using the
register (or
). When a particular event is not enabled (for example
[x] = 0), the correspondent status (
[x] = 1) bit is flagged if the
correspondent event occurs. This has no effect on the interrupt line, but can be used by software to poll
the status.
The SBL flags no read buffer logic underflow events. These are signaled by the reading module.
lists the read port and corresponding events if they exist.
Table 6-78. Camera ISP Central-Resource SBL Read-Buffer Underflow Events
Read port
Description
CCDC faulty pixel
When faulty-pixel correction is used, the pixel frequency is
imposed by the camera clock. This imposes read-time
constraints to the faulty-pixel table read. When the table read
was too slow, the
[16] FPERR bit is set to 1 and no
more faulty pixels are processed for that frame. This error
generates an interrupt that can be mapped to DSP or ARM by
setting the CCDC_ERR_IRQ bit in the
register (or
). To clear this interrupt, clear the
[16] FPERR bit before clearing the
[11] CCDC_ERR_IRQ bit (or
).
CCDC lens-shading compensation
There must be adequate memory bandwidth if this feature is
enabled. If the data fetched from memory arrives late, then the
CCDC_LSC_PREFETCH_ERROR event is triggered and an
interrupt generated.
Preview dark frame
There must be adequate memory bandwidth if this feature is
enabled. If the data fetched from memory arrives late, the
[31] DRK_FAIL status bit is set to indicate a fail. No
interrupt is generated by this event.
Preview image from memory
No error can occur on this port because the preview module
stops processing when no image data is ready.
1296Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated