Public Version
www.ti.com
Camera ISP Functional Description
6.4.6.1.3.4 Camera ISP CCDC Data Formatter, Lens-Shading Compensation, and Video-Port Interface
NOTE:
For YUV data, the data formatter, lens-shading compensation, and video-port interface must
be bypassed (
[15] VPEN = 0x0 and
[18] VP2SDR =
0x0).
The data-formatter module can be enabled to rearrange data after the faulty-pixel correction operation. It
is intended to be used:
•
When output data lines from the CCDC include pixels from multiple resolution lines. Internally, these
sensors combine pixels from multiple horizontal lines into one output pseudoline.
•
To smooth bandwidth. This helps reduce peak bandwidth when image cropping is used with the
Resizer.
The reformatter module performs the decomposition before the remainder of the normal CCDC processing
stages.
The lens-shading compensation (LSC) module can be placed at two different locations:
•
Before the data reformatter. It can only be used for Bayer sensors. The H3A video port gets the
shading corrected image.
•
After the data reformatter. This setup is required for non-Bayer sensors. Histogram and preview
modules get the shading corrected image; however, H3A receives a non-corrected image.
Video-port/data-formatter output can also be saved to memory (instead of the RAW data). When
[18] VP2SDR is set to 1, video-port data is sent to the output formatter. In addition,
the
[17] WEN bit must be enabled to store the output to memory.
The data-formatter and video-port interfaces are only 10 bits wide; therefore, the input data must be
adjusted as it enters these modules. For flexibility, the bits to be retained can be selected by
[14:12] VPIN.
The reformatter decomposes each input line into multiple output lines with new, internally generated
HS/VS signals. The reformatter sends it to memory or to other camera ISP modules. These new HS/VS
signals, rather than the original sensor HS/VS signals, then gate the downstream processing.
Conversion Area Select Parameters
When the data formatter is enabled, HS/VS signals are still generated as output (
[16]
VDHDEN = 0x1). The settings for these output signals are in the following fields:
•
[27:16] HDW
•
[11:0] VDW
•
[31:16] PPLN
•
[15:0] HLPRF
NOTE:
These four registers are not used when HS/VS signals are input signals
[16] VDHDEN = 0x0).
NOTE:
The settings reflect those for the sensor readout frame, not the resultant reformatted frame.
Registers
and
affect the input framing even if data formatter is
disabled.
Registers
,
, and
control the output
formatter framing. It is used only when the CCDC output is sent to memory.
shows the data formatter conversion area selection.
1197
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated
