Texas Instruments OMAP-L138 C6000 Manual Download Page 271

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Summary of Contents for OMAP-L138 C6000

Page 1: ...Supports up to Four SP Additions Per Clock Four DP Additions Every Two Clocks Supports up to Two Floating Point SP or DP Reciprocal Approximation RCPxP and Square Root Reciprocal Approximation RSQRxP...

Page 2: ...Compliant MII Media Independent Interface RMII Reduced Media Independent Interface Management Data I O MDIO Module Video Port Interface VPIF Two 8 Bit SD BT 656 Single 16 Bit or Single Raw 8 10 and 1...

Page 3: ...peration with known trusted code Basic Secure Boot uses either SHA 1 or SHA 256 and AES 128 for boot image validation Basic Secure Boot also uses AES 128 for boot image encryption The secure boot flow...

Page 4: ...as well as START ENABLE and WAIT signals to provide control for a variety of data converters A video port interface VPIF provides a flexible video I O port The rich peripheral set provides the ability...

Page 5: ...PWM x2 eCAP x3 EMIFA 8b 16B NAND Flash 16b SDRAM DDR2 MDDR Controller RTC 32 kHz OSC I C x2 2 SPI x2 UART x3 McBSP x2 Video VPIF Parallel Port uPP EMAC 10 100 MII RMII MDIO USB1 1 OHCI Ctlr PHY USB2 0...

Page 6: ...PSC 96 6 9 Enhanced Direct Memory Access Controller EDMA3 101 6 10 External Memory Interface A EMIFA 107 6 11 DDR2 mDDR Memory Controller 119 6 12 Memory Protection Units 132 6 13 MMC SD SDIO MMCSD0...

Page 7: ...ncorporated 2 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from March 31 2014 to January 31 2017 Page Removed internal pullup d...

Page 8: ...annel Audio Serial Port McASP 1 each with transmit receive FIFO buffer 16 serializers Multichannel Buffered Serial Port McBSP 2 each with transmit receive FIFO buffer 16 10 100 Ethernet MAC with Manag...

Page 9: ...ction processing does not necessarily include testing of all parameters Voltage Core V Variable 1 2V 1 0V for 375 MHz version Variable 1 3V 1 0V for 456 MHz version I O V 1 8V or 3 3 V Packages 13 mm...

Page 10: ...s as shown in Figure 3 2 The two general purpose register files A and B each contain 32 32 bit registers for a total of 64 registers The general purpose registers can be used for data or can be data a...

Page 11: ...throughput the S unit allows sustained high performance for the quad 8 bit 16 bit and dual 16 bit instructions Unpack instructions prepare 8 bit data for parallel 16 bit operations Pack instructions...

Page 12: ...x 1x 32 LSB 32 MSB 32 LSB 32 MSB dst2 B B A 8 8 8 8 32 32 32 32 C C Even register file A A0 A2 A4 A30 Even register file B B0 B2 B4 B30 D D D D A On M unit dst2 is 32 MSB B On M unit dst1 is 32 LSB C...

Page 13: ...both Table 3 2 shows a memory map of the C674x CPU cache registers for the device Table 3 2 C674x Cache Registers Byte Address Register Name Register Description 0x0184 0000 L2CFG L2 Cache configurat...

Page 14: ...emory Attribute Registers for EMIFA Async Data CS3 External memory addresses 0x6200 0000 0x63FF FFFF 0x0184 8190 0x0184 8197 MAR100 MAR101 Memory Attribute Registers for EMIFA Async Data CS4 External...

Page 15: ...081 7FFF 0x0184 A230 L2MPPA12 L2 memory protection page attribute register 12 controls memory address 0x0081 8000 0x0081 9FFF 0x0184 A234 L2MPPA13 L2 memory protection page attribute register 13 contr...

Page 16: ...3 8000 0x0073 FFFF 0x0184 A2A0 L2MPPA40 L2 memory protection page attribute register 40 controls memory address 0x0074 0000 0x0074 7FFF 0x0184 A2A4 L2MPPA41 L2 memory protection page attribute registe...

Page 17: ...n fault command register 0x0184 A40C 0x0184 A4FF Reserved 0x0184 A500 L1PMPLK0 L1P memory protection lock key bits 31 0 0x0184 A504 L1PMPLK1 L1P memory protection lock key bits 63 32 0x0184 A508 L1PMP...

Page 18: ...ction lock key command register 0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register 0x0184 AD18 0x0184 ADFF Reserved 0x0184 AE00 0x0184 AE3F Reserved 2 0x0184 AE40 L1DMPPA16 L1D mem...

Page 19: ...orporated Table 3 3 C674x L1 L2 Memory Protection Registers continued HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 AE78 L1DMPPA30 L1D memory protection page attribute register 30 controls mem...

Page 20: ...000 0x017F FFFF 0x0180 0000 0x0180 FFFF 64K DSP Interrupt Controller 0x0181 0000 0x0181 0FFF 4K DSP Powerdown Controller 0x0181 1000 0x0181 1FFF 4K DSP Security ID 0x0181 2000 0x0181 2FFF 4K DSP Revis...

Page 21: ...5000 0x01E1 5FFF 4K Memory Protection Unit 2 MPU 2 0x01E1 6000 0x01E1 6FFF 4K UPP 0x01E1 7000 0x01E1 7FFF 4K VPIF 0x01E1 8000 0x01E1 9FFF 8K SATA 0x01E1 A000 0x01E1 AFFF 4K PLL Controller 1 0x01E1 B00...

Page 22: ...1170 0000 0x117F FFFF 1024K DSP L2 ROM 1 0x1180 0000 0x1183 FFFF 256K DSP L2 RAM 0x1184 0000 0x11DF FFFF 0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM 0x11E0 8000 0x11EF FFFF 0x11F0 0000 0x11F0 7FFF 32K DSP...

Page 23: ..._D 9 UPP_XD 1 GP7 1 BOOT 1 VP_DOUT 10 LCD_D 10 UPP_XD 2 GP7 2 BOOT 2 VP_DOUT 11 LCD_D 11 UPP_XD 3 GP7 3 BOOT 3 VP_DOUT 6 LCD_D 6 UPP_XD 14 GP7 14 PRU1_R31 14 VP_DOUT 7 LCD_D 7 UPP_XD 15 GP7 15 PRU1_R3...

Page 24: ...0 USB0_VDDA12 TDI NC PRU0_R30 26 UHPI_HR UPP_CHA_WAIT GP6 8 PRU1_R31 17 W VP_DIN 12 UHPI_HD 4 UPP_D 4 PRU0_R30 12 PRU0_R31 12 RESETOUT UHPI_HAS PRU1_R30 14 GP6 15 RSV2 GP8 0 OSCOUT DDR_D 0 PRU0_R30 2...

Page 25: ...PI0_SCS 3 UART0_CTS GP8 2 MII_RXD 1 SATA_MP_SWITCH SPI0_SCS 0 TM64P1_OUT12 GP1 6 MDIO TM64P1_IN12 SPI0_SOMI EPWMSYNCI GP8 6 MII_RXER SPI0_SCS 2 UART0_RTS GP8 1 MII_RXD 0 SATA_CP_DET SPI1_SCS 7 I2C0_SC...

Page 26: ...NABLE GP8 13 PRU1_R31 25 AHCLKR GP0 11 PRU0_R31 18 PRU0_R30 18 UART1_RTS EMA_D 12 GP3 4 EMA_WEN_DQM 0 GP2 3 EMA_CLK PRU0_R30 5 GP2 7 PRU0_R31 5 AXR6 CLKR0 GP1 14 MII_TXEN PRU0_R31 6 AXR11 FSX1 GP0 3 E...

Page 27: ...r 1 8V nominal The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage Group A operates at the voltage of power supply DVDD3318_A Group B o...

Page 28: ...al is part of a dual voltage IO group A B or C These groups can be operated at 3 3V or 1 8V nominal The three groups can be operated at independent voltages but all pins withina group will operate at...

Page 29: ...ions SIGNAL TYPE 1 PULL 2 POWER GROUP 3 DESCRIPTION NAME NO RTC_XI J19 I RTC 32 kHz oscillator input RTC_XO H19 O RTC 32 kHz oscillator output RTC_ALARM UART2_CTS GP0 8 DEEPSLEEP F4 O CP 0 A RTC Alarm...

Page 30: ...quires a pull up an external pull up can be used For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see the Device Configur...

Page 31: ...12 PRU1_R30 20 GP5 12 PRU1_R31 20 D13 O CP 19 B EMA_A 11 PRU1_R30 19 GP5 11 PRU1_R31 19 B12 O CP 19 B EMIFA address bus EMA_A 10 PRU1_R30 18 GP5 10 PRU1_R31 18 C12 O CP 19 B EMA_A 9 PRU1_R30 17 GP5 9...

Page 32: ...ions continued SIGNAL TYPE 1 PULL 2 POWER GROUP 3 DESCRIPTION NAME NO EMA_WE GP3 11 B9 O CP 16 B EMIFA SDRAM write enable EMA_WEN_DQM 1 GP2 2 A5 O CP 16 B EMIFA write enable data mask for EMA_D 15 8 E...

Page 33: ...lup pulldown resistors and situations where external pullup pulldown resistors are required see the Device Configuration section For electrical specifications on pullup and internal pulldown circuits...

Page 34: ...V8 O IPD DDR_DQGATE0 R11 O IPD DDR2 loopback signal for external DQS gating Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data DDR_DQGATE1 R12 I IPD DDR2 loopba...

Page 35: ...nominal The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage Group A operates at the voltage of power supply DVDD3318_A Group B operate...

Page 36: ...electrical specifications on pullup and internal pulldown circuits see the Device Operating Conditions section 3 This signal is part of a dual voltage IO group A B or C These groups can be operated a...

Page 37: ...D 5 PRU0_R30 13 PRU0_R31 13 U19 O CP 27 C VP_DIN 12 UHPI_HD 4 UPP_D 4 PRU0_R30 12 PRU0_R31 12 T16 O CP 27 C VP_DIN 11 UHPI_HD 3 UPP_D 3 PRU0_R30 11 PRU0_R31 11 R18 O CP 27 C VP_DIN 10 UHPI_HD 2 UPP_D...

Page 38: ...12 PRU0_R31 19 B2 I CP 0 A AHCLKR PRU0_R30 18 UART1_RTS GP0 11 PRU0_R31 18 A2 I CP 0 A AHCLKX USB_REFCLKIN UART1_CTS GP0 10 PRU0_R31 17 A3 I CP 0 A AMUTE PRU0_R30 16 UART2_RTS GP0 9 PRU0_R31 16 D5 I C...

Page 39: ...2 PRU1_R30 20 GP5 12 PRU1_R31 20 D13 O CP 19 B EMA_A 11 PRU1_R30 19 GP5 11 PRU1_R31 19 B12 O CP 19 B EMA_A 10 PRU1_R30 18 GP5 10 PRU1_R31 18 C12 O CP 19 B EMA_A 9 PRU1_R30 17 GP5 9 D12 O CP 19 B EMA_A...

Page 40: ...RU1_R30 19 GP5 11 PRU1_R31 19 B12 I CP 19 B EMA_A 10 PRU1_R30 18 GP5 10 PRU1_R31 18 C12 I CP 19 B PRU0_R30 26 UHPI_HRW UPP_CHA_WAIT GP6 8 PRU1_R31 17 T15 I CP 24 C VP_CLKIN1 UHPI_HDS1 PRU1_R30 9 GP6 6...

Page 41: ...plication requires a pull up an external pull up can be used For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see the Dev...

Page 42: ...on pullup pulldown resistors and situations where external pullup pulldown resistors are required see the Device Configuration section For electrical specifications on pullup and internal pulldown cir...

Page 43: ...sociated with these registers are pulled down If the application requires a pull up an external pull up can be used For more detailed information on pullup pulldown resistors and situations where exte...

Page 44: ...p and internal pulldown circuits see the Device Operating Conditions section 3 This signal is part of a dual voltage IO group A B or C These groups can be operated at 3 3V or 1 8V nominal The three gr...

Page 45: ...ring reset all of the pins associated with these registers are pulled down If the application requires a pull up an external pull up can be used For more detailed information on pullup pulldown resist...

Page 46: ...iled information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see the Device Configuration section For electrical specifications on pullup and inte...

Page 47: ...ge IO group A B or C These groups can be operated at 3 3V or 1 8V nominal The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage Group A o...

Page 48: ...For electrical specifications on pullup and internal pulldown circuits see the Device Operating Conditions section 3 This signal is part of a dual voltage IO group A B or C These groups can be operate...

Page 49: ...nd internal pulldown circuits see the Device Operating Conditions section 3 This signal is part of a dual voltage IO group A B or C These groups can be operated at 3 3V or 1 8V nominal The three group...

Page 50: ...n pullup and internal pulldown circuits see the Device Operating Conditions section 3 This signal is part of a dual voltage IO group A B or C These groups can be operated at 3 3V or 1 8V nominal The t...

Page 51: ...I CP 26 C EMAC RMII receiver error VP_DIN 3 UHPI_HD 11 UPP_D 11 RMII_RXD 0 PRU0_R31 25 V17 I CP 26 C EMAC RMII receive data VP_DIN 4 UHPI_HD 12 UPP_D 12 RMII_RXD 1 PRU0_R31 26 W16 I CP 26 C VP_DIN 0...

Page 52: ...r 1 8V nominal The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage Group A operates at the voltage of power supply DVDD3318_A Group B o...

Page 53: ...nominal The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage Group A operates at the voltage of power supply DVDD3318_A Group B operates...

Page 54: ...ce Configuration section For electrical specifications on pullup and internal pulldown circuits see the Device Operating Conditions section 3 This signal is part of a dual voltage IO group A B or C Th...

Page 55: ...t the voltage of power supply DVDD3318_A Group B operates at the voltage of power supply DVDD3318_B Group C operates at the voltage of power supply DVDD3318_C 3 7 22 Universal Host Port Interface UHPI...

Page 56: ...as Instruments Incorporated Table 3 26 Universal Host Port Interface UHPI Terminal Functions continued SIGNAL TYPE 1 PULL 2 POWER GROUP 3 DESCRIPTION NAME NO PRU0_R30 30 UHPI_HINT PRU1_R30 11 GP6 12 R...

Page 57: ...up pulldown resistors are required see the Device Configuration section For electrical specifications on pullup and internal pulldown circuits see the Device Operating Conditions section 3 This signal...

Page 58: ...BOOT 3 T3 I O CP 29 C VP_DOUT 10 LCD_D 10 UPP_XD 2 GP7 2 BOOT 2 T2 I O CP 29 C VP_DOUT 9 LCD_D 9 UPP_XD 1 GP7 1 BOOT 1 T1 I O CP 29 C VP_DOUT 8 LCD_D 8 UPP_XD 0 GP7 0 BOOT 0 U3 I O CP 29 C VP_DIN 7 UH...

Page 59: ...roups can be operated at 3 3V or 1 8V nominal The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage Group A operates at the voltage of po...

Page 60: ...T 15 LCD_D 15 UPP_XD 7 GP7 7 BOOT 7 P4 O CP 29 C VPIF display data bus VP_DOUT 14 LCD_D 14 UPP_XD 6 GP7 6 BOOT 6 R3 O CP 29 C VP_DOUT 13 LCD_D 13 UPP_XD 5 GP7 5 BOOT 5 R2 O CP 29 C VP_DOUT 12 LCD_D 12...

Page 61: ...and situations where external pullup pulldown resistors are required see the Device Configuration section For electrical specifications on pullup and internal pulldown circuits see the Device Operatin...

Page 62: ...XCLK D3 I O CP 5 A AXR4 FSR0 GP1 12 MII_COL D1 I O CP 5 A AXR3 FSX0 GP1 11 MII_TXD 3 E3 I O CP 5 A AXR2 DR0 GP1 10 MII_TXD 2 E2 I O CP 5 A AXR1 DX0 GP1 9 MII_TXD 1 E1 I O CP 5 A SPI0_CLK EPWM0A GP1 8...

Page 63: ...5 GP2 7 PRU0_R31 5 B7 I O CP 16 B EMA_SDCKE PRU0_R30 4 GP2 6 PRU0_R31 4 D8 I O CP 16 B EMA_RAS PRU0_R30 3 GP2 5 PRU0_R31 3 A16 I O CP 16 B EMA_CAS PRU0_R30 2 GP2 4 PRU0_R31 2 A9 I O CP 16 B EMA_WEN_D...

Page 64: ...4 A11 I O CP 18 B EMA_A 19 MMCSD0_DAT 2 PRU1_R30 27 GP4 3 C10 I O CP 18 B EMA_A 18 MMCSD0_DAT 3 PRU1_R30 26 GP4 2 E11 I O CP 18 B EMA_A 17 MMCSD0_DAT 4 PRU1_R30 25 GP4 1 B11 I O CP 18 B EMA_A 16 MMCSD...

Page 65: ...0 3 GP6 4 PRU1_R31 4 H3 I O CP 30 C VP_CLKOUT2 MMCSD1_DAT 2 PRU1_R30 2 GP6 3 PRU1_R31 3 K3 I O CP 30 C VP_CLKIN3 MMCSD1_DAT 1 PRU1_R30 1 GP6 2 PRU1_R31 2 J3 I O CP 30 C VP_CLKOUT3 PRU1_R30 0 GP6 1 PRU...

Page 66: ...CP30 C GPIO Bank 8 PRU0_R30 24 MMCSD1_CLK UPP_CHB_START GP8 14 PRU1_R31 26 G2 I O CP 30 C PRU0_R30 23 MMCSD1_CMD UPP_CHB_ENABLE GP8 13 PRU1_R31 25 J4 I O CP 30 C PRU0_R30 22 PRU1_R30 8 UPP_CHB_WAIT G...

Page 67: ...tage 3 7 26 Reserved and No Connect Table 3 30 Reserved and No Connect Terminal Functions SIGNAL TYPE 1 DESCRIPTION NAME NO RSV2 T19 PWR Reserved For proper device operation this pin must be tied eith...

Page 68: ...d at 3 3V DVDD3318_A I O supply F5 F15 G5 G14 G15 H5 PWR 1 8V or 3 3 V dual voltage LVCMOS I O supply voltage pins Group A DVDD3318_B I O supply E14 F6 F7 F8 F10 F11 F12 F13 G9 J14 K15 PWR 1 8V or 3 3...

Page 69: ...tput connected to an external 0 22 F filter capacitor USB1_DM No Connect VSS or No Connect Use as USB1 function USB1_DP No Connect VSS or No Connect Use as USB1 function USB1_VDDA33 No Connect No Conn...

Page 70: ...of 25mA can result on the 1 8V supply To minimize power consumption the DDR2 mDDR controller input receivers should be placed in power down mode by setting VTPIO 14 1 Table 3 35 Unused DDR2 mDDR Memor...

Page 71: ...t Loader The following boot modes are supported NAND Flash boot 8 bit NAND 16 bit NAND supported on ROM revisions after d800k002 see the bootloader documents mentioned above to determine the ROM revis...

Page 72: ...1CFG Host 1 Configuration Register 0x01C1 40E0 IRAWSTAT Interrupt Raw Status Set Register Privileged mode 0x01C1 40E4 IENSTAT Interrupt Enable Status Clear Register Privileged mode 0x01C1 40E8 IENSET...

Page 73: ...9 Register Privileged mode 0x01C1 4170 SUSPSRC Suspend Source Register Privileged mode 0x01C1 4174 CHIPSIG Chip Signal Register 0x01C1 4178 CHIPSIG_CLR Chip Signal Clear Register 0x01C1 417C CFGCHIP0...

Page 74: ...leakage currents of all the devices connected to the net as well as any internal pullup or pulldown resistors Decide a target value for the net For a pulldown resistor this should be below the lowest...

Page 75: ...t DVDD 30 up to 30 of Signal Period USB 5V Tolerant IOs USB0_DM USB0_DP USB0_ID USB1_DM USB1_DP 5 25V 3 USB0 VBUS Pin 5 50V 3 Output voltage VO ranges Dual voltage LVCMOS outputs 3 3V or 1 8V Steady S...

Page 76: ...L0_VDDA PLL0 Supply Voltage 1 14 1 2 1 32 V PLL1_VDDA PLL1 Supply Voltage 1 14 1 2 1 32 V SATA_VDD SATA Core Logic Supply Voltage 1 14 1 2 1 32 V USB_CVDD USB0 USB1 Core Logic Supply Voltage 1 14 1 2...

Page 77: ...al charge pump input 0 5 25 V Differential Clock Input Voltage Differential input voltage SATA_REFCLKP and SATA_REFCLKN 250 2000 mV Transition Time tt Transition time 10 90 All Inputs unless otherwise...

Page 78: ...To avoid significant degradation the device power on hours POH must be limited to the following Table 5 1 Recommended Power On Hours Silicon Revision Speed Grade Operating Junction Temperature Tj Nom...

Page 79: ...al Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature Unless Otherwise Noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High level output voltage dual vol...

Page 80: ...ed as a load only It is not necessary to add or subtract the transmission line delay 2 ns or longer from the data sheet timings Input requirements in this data sheet are tested with an input slew rate...

Page 81: ...on the device groups 2a and 2b can be controlled from the same power supply and powered up together 3 All static 1 8V IO supplies DVDD18 DDR_DVDD18 USB0_VDDA18 USB1_VDDA18 and SATA_VDDR and any of th...

Page 82: ...ays be asserted upon power up and the device s internal emulation logic will always be properly initialized JTAG controllers from Texas Instruments actively drive TRST high However some third party JT...

Page 83: ...ubmit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated The RTC peripheral is not reset du...

Page 84: ...et the reset timings in this table refer to RESET only TRST is held high 3 OSCIN cycles 6 4 3 Reset Electrical Data Timings Table 6 1 assumes testing over the recommended operating conditions Table 6...

Page 85: ...5 85 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009...

Page 86: ...frequencies between 12 and 20 MHz a crystal with 80 ohm max ESR is recommended For input clock frequencies between 20 and 30 MHz a crystal with 60 ohm max ESR is recommended Typical load capacitance...

Page 87: ...s tt OSCIN Transition time OSCIN 0 25P or 10 1 ns tj OSCIN Period jitter OSCIN 0 02P ns 6 6 Clock PLLs The device has two PLL controllers that provide clocks to different parts of the system PLL0 prov...

Page 88: ...gure 6 8 Figure 6 8 PLL External Filtering Components The external filtering components shown above provide noise immunity for the PLLs PLL0_VDDA and PLL1_VDDA should not be connected together to prov...

Page 89: ...LEN PLLCTL CLKMODE POSTDIV PLLC0 OBSCLK CLKOUT Pin DIV4 5 OSCDIV PLL Controller 0 PLL Controller 1 SYSCLK2 SYSCLK3 SYSCLK1 OSCIN 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYS...

Page 90: ...multiply factors within the PLLs and post division for each of the chip level clocks from the PLLs outputs PLLC0 also controls reset propagation through the chip clock alignment and test points PLLC0...

Page 91: ...voltage operating points Table 6 5 Maximum Internal Clock Frequencies at Each Voltage Operating Point CLOCK SOURCE CLOCK DOMAIN 1 3V NOM 1 2V NOM 1 1V NOM 1 0V NOM PLL0_SYSCLK1 DSP subsystem 456 MHz 3...

Page 92: ...4P0_TINT12 Timer64P0 TINT12 5 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register 6 PRU_EVTOUT0 PRUSS Interrupt 7 EHRPWM0 HiResTimer PWM0 Interrupt 8 EDMA3_0_CC0_INT1 EDMA3_0 Channel Controller 0 Shadow Region 1...

Page 93: ...INT EMIFA 56 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt 57 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt 58 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Err...

Page 94: ...mit Interrupt 89 MCBSP1_RINT McBSP1 Receive Interrupt 90 MCBSP1_XINT McBSP1 Transmit Interrupt 91 EDMA3_1_CC0_INT1 EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt 92 EDMA3_1...

Page 95: ...MASK1 Event mask register 1 0x0180 0088 EVTMASK2 Event mask register 2 0x0180 008C EVTMASK3 Event mask register 3 0x0180 00A0 MEVTFLAG0 Masked event flag register 0 0x0180 00A4 MEVTFLAG1 Masked event...

Page 96: ...ror Pending Register 0 module 0 31 PSC1 0x01C1 0050 0x01E2 7050 MERRCR0 Module Error Clear Register 0 module 0 15 PSC0 Module Error Clear Register 0 module 0 31 PSC1 0x01C1 0060 0x01E2 7060 PERRPR Pow...

Page 97: ...ter 0x01C1 0A04 0x01E2 7A04 MDCTL1 Module 1 Control Register 0x01C1 0A08 0x01E2 7A08 MDCTL2 Module 2 Control Register 0x01C1 0A0C 0x01E2 7A0C MDCTL3 Module 3 Control Register 0x01C1 0A10 0x01E2 7A10 M...

Page 98: ...9 and Table 6 10 lists the set of peripherals modules that are controlled by the PSC the power domain they are associated with the LPSC assignment and the default power on reset module states The modu...

Page 99: ...PIF AlwaysON PD0 SwRstDisable 10 SPI 1 AlwaysON PD0 SwRstDisable 11 I2C 1 AlwaysON PD0 SwRstDisable 12 UART 1 AlwaysON PD0 SwRstDisable 13 UART 2 AlwaysON PD0 SwRstDisable 14 McBSP0 McBSP0 FIFO Always...

Page 100: ...t Asserted On A module state in the SyncReset state has its module reset asserted and it has its clock on Generally software is not expected to initiate this state SwRstDisable Asserted Off A module i...

Page 101: ...5 McBSP1 Transmit 21 PRU_EVTOUT7 6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt 7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt 8 UART0 Receive 24 I2C0 Receive 9 UART0 Transmit 25 I2C0 Transmit 10...

Page 102: ...NUM0 DMA Channel Queue Number Register 0 0x01C0 0244 0x01E3 0244 DMAQNUM1 DMA Channel Queue Number Register 1 0x01C0 0248 0x01E3 0248 DMAQNUM2 DMA Channel Queue Number Register 2 0x01C0 024C 0x01E3 02...

Page 103: ...C0 1084 0x01E3 1084 QEER QDMA Event Enable Register 0x01C0 1088 0x01E3 1088 QEECR QDMA Event Enable Clear Register 0x01C0 108C 0x01E3 108C QEESR QDMA Event Enable Set Register 0x01C0 1090 0x01E3 1090...

Page 104: ...ter 0x01C0 2294 0x01E3 2294 QSECR QDMA Secondary Event Clear Register 0x01C0 4000 0x01C0 4FFF 0x01E3 4000 0x01E3 4FFF Parameter RAM PaRAM Table 6 14 EDMA3 Transfer Controller EDMA3TC Registers EDMA3_0...

Page 105: ...ster 2 0x01C0 8384 0x01C0 8784 0x01E3 8384 DFSRC2 Destination FIFO Source Address Register 2 0x01C0 8388 0x01C0 8788 0x01E3 8388 DFCNT2 Destination FIFO Count Register 2 0x01C0 838C 0x01C0 878C 0x01E3...

Page 106: ...nstruments Incorporated Table 6 16 Parameter Set Entries OFFSET BYTE ADDRESS WITHIN THE PARAMETER SET ACRONYM PARAMETER ENTRY 0x0000 OPT Option 0x0004 SRC Source Address 0x0008 A_B_CNT A Count B Count...

Page 107: ...Write cycle timings setup hold strobe Bus turn around time Extended Wait Option With Programmable Timeout Select Strobe Option NAND flash controller supports 1 bit and 4 bit ECC calculation on blocks...

Page 108: ...6 1024 2 16 16 10 1 1024 128 512 2 16 16 10 2 2048 256 1024 2 16 16 10 4 4096 512 2048 2 16 16 11 1 2048 256 1024 2 16 16 11 2 4096 512 2048 2 16 15 11 4 4096 512 2048 6 10 3 EMIFA SDRAM Loading Limit...

Page 109: ...k Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated A likely use case with more than one EMIFA chip select used f...

Page 110: ...B R 2 B NAND FLASH x8 MultiPlane DVDD EMA_WAIT EMA_CS 4 EMA_CS 5 110 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folder Links TMS320C6748 Perip...

Page 111: ...r 0x6800 0040 INTRAW EMIFA Interrupt Raw Register 0x6800 0044 INTMSK EMIFA Interrupt Mask Register 0x6800 0048 INTMSKSET EMIFA Interrupt Mask Set Register 0x6800 004C INTMSKCLR EMIFA Interrupt Mask Cl...

Page 112: ...toh CLKH CSIV Output hold time EMA_CLK rising to EMA_CS 0 invalid 1 1 1 ns 5 td CLKH DQMV Delay time EMA_CLK rising to EMA_WE_DQM 1 0 valid 7 9 5 13 ns 6 toh CLKH DQMIV Output hold time EMA_CLK rising...

Page 113: ...8 12 10 16 3 5 7 7 11 13 15 9 BASIC SDRAM WRITE OPERATION EMA_CS 0 EMA_WE_DQM 1 0 EMA_RAS EMA_CAS EMA_WE 113 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedbac...

Page 114: ...ed during the STROBE phase However cycles inserted as part of this extended wait period should not be counted the 4E requirement is to the start of where the HOLD phase would begin if there were no ex...

Page 115: ...OEH EMCEH Output hold time EMA_OE high to EMA_CE 5 2 high SS 0 RH E 3 RH E RH E 3 ns Output hold time EMA_OE high to EMA_CE 5 2 high SS 1 3 0 3 ns 6 tsu EMBAV EMOEL Output setup time EMA_BA 1 0 valid...

Page 116: ...23 th EMWEH EMAIV Output hold time EMA_WE high to EMA_A 13 0 invalid WH E 3 WH E WH E 3 ns 24 tw EMWEL EMA_WE active low width EW 0 WST E 3 WST E WST E 3 ns EMA_WE active low width EW 1 WST EWC E 3 WS...

Page 117: ...0 5 9 7 4 8 3 1 EMA_ _DQM 1 0 WE EMA_A_RW 1 6 28 29 SETUP STROBE HOLD 117 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748...

Page 118: ...ended Due to EMA_WAIT STROBE HOLD 14 EMA_A_RW 118 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information a...

Page 119: ...M Mobile DDR SDRAM 256 MByte memory space for DDR2 256 MByte memory space for mDDR CAS latencies DDR2 2 3 4 and 5 mDDR 2 and 3 Internal banks DDR2 1 2 4 and 8 mDDR 1 2 and 4 Burst length 8 Burst type...

Page 120: ...Counter Master Region Select Register 0xB000 0050 PCT Performance Counter Time Register 0xB000 00C0 IRR Interrupt Raw Register 0xB000 00C4 IMR Interrupt Mask Register 0xB000 00C8 IMSR Interrupt Mask S...

Page 121: ...T T T T T T T T T T T T T T T T T T T T T T T T T T VREF 3 T Terminator if desired See terminator comments 0 1 F 2 DDR_DQS 0 NC 1 121 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Sub...

Page 122: ...DDR_CKE CKE T DDR_DQM1 DM T DDR_DQS1 DQS T NC NC 1 122 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Informa...

Page 123: ...routing the device is a six layer stack as shown in Table 6 26 Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint Complete st...

Page 124: ...d they are separated from DDR2 mDDR routing layers by a ground plane 5 w PCB trace width as defined in Table 6 27 6 11 3 4 Placement Figure 6 19 shows the required placement for the device as well as...

Page 125: ...plane should cover the entire keep out region 125 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information...

Page 126: ...An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board 3 These devices should be placed as close as possible to the device being bypass...

Page 127: ...R_RAS DDR_WE DDR_CKE D0 DQS0 DDR_D 7 0 DDR_DQM0 D1 DQS1 DDR_D 15 8 DDR_DQM1 DQGATE CK DQS0 DQS1 DDR_DQGATE0 DDR_DQGATE1 1 Only series termination is permitted parallel or SST specifically disallowed 2...

Page 128: ...om Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated 6 11 3 10 VREF Routing VREF is...

Page 129: ...nd ADDR_CTRL net classes The route is a balanced T as it is intended that the length of segments B and C be equal In addition the length of A should be maximized Figure 6 23 CK and ADDR_CTRL Routing a...

Page 130: ...s i e from DQS0 and data byte 0 to DQS1 and data byte 1 5 D s from other DQS domains are considered other DDR2 mDDR trace 6 DQLM is the longest Manhattan distance of each of the DQS and D net class Fi...

Page 131: ...ER MIN TYP MAX UNIT 1 DQGATE Length F CKB0B 1 2 Center to center DQGATE to any other trace spacing 4w 2 3 DQS D nominal trace length DQLM 50 DQLM DQLM 50 Mils 4 DQGATE Skew 3 100 Mils 6 11 3 12 DDR2 m...

Page 132: ...4 CONFIG Configuration 0x01E1 4010 IRAWSTAT Interrupt raw status set 0x01E1 4014 IENSTAT Interrupt enable status clear 0x01E1 4018 IENSET Interrupt enable 0x01E1 401C IENCLR Interrupt enable clear 0x0...

Page 133: ...protection attributes 0x01E1 521C 0x01E1 521F Reserved 0x01E1 5220 PROG3_MPSAR Programmable range 3 start address 0x01E1 5224 PROG3_MPEAR Programmable range 3 end address 0x01E1 5228 PROG3_MPPA Progr...

Page 134: ...e range 10 start address 0x01E1 5294 PROG10_MPEAR Programmable range 10 end address 0x01E1 5298 PROG10_MPPA Programmable range 10 memory page protection attributes 0x01E1 529C 0x01E1 529F Reserved 0x0...

Page 135: ...1 B008 MMCST0 MMC Status Register 0 0x01C4 000C 0x01E1 B00C MMCST1 MMC Status Register 1 0x01C4 0010 0x01E1 B010 MMCIM MMC Interrupt Mask Register 0x01C4 0014 0x01E1 B014 MMCTOR MMC Response Time Out...

Page 136: ...SD_CLK high 2 5 2 5 2 5 ns 3 tsu DATV CLKH Setup time MMCSD_DATx valid before MMCSD_CLK high 4 5 5 6 ns 4 th CLKH DATV Hold time MMCSD_DATx valid after MMCSD_CLK high 2 5 2 5 2 5 ns Table 6 41 Switchi...

Page 137: ...MD 13 7 10 9 13 13 13 137 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specificat...

Page 138: ...a pointer to a descriptor table for transferring data between system memory and the device The SATA Controller supports the following features Serial ATA 1 5 Gbps Gen 1i and 3 Gbps Gen 2i line speeds...

Page 139: ...E1 80B0 BISTDECR BIST DWORD Error Count Register 0x01E1 80E0 TIMER1MS BIST DWORD Error Count Register 0x01E1 80E8 GPARAM1R Global Parameter 1 Register 0x01E1 80EC GPARAM2R Global Parameter 2 Register...

Page 140: ...manufacturing specification The design rules constrain PCB trace length PCB trace skew signal integrity cross talk and signal timing TI has performed the simulation and system design work to ensure th...

Page 141: ...tance between planes and dielectric material Verify with a proper PCB manufacturing tool that the trace geometry for both data signal pairs results in exactly 100 ohms differential impedance traces Ta...

Page 142: ...ace is not used the SATA signals should be configured as shown below Table 6 48 Unused SATA Signal Configuration SATA Signal Name Configuration if SATA peripheral is not used SATA_RXP No Connect SATA_...

Page 143: ...ral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated 6 15 Multichannel Audio Serial Port McASP The McASP serial port is specifically designed for multichann...

Page 144: ...ias of GBLCTL only receive bits are affected allows receiver to be reset independently from transmitter 0x01D0 0064 RMASK Receive format unit bit mask register 0x01D0 0068 RFMT Receive bit stream form...

Page 145: ...013C DITUDRA3 Left even TDM time slot channel user data register DIT mode 3 0x01D0 0140 DITUDRA4 Left even TDM time slot channel user data register DIT mode 4 0x01D0 0144 DITUDRA5 Left even TDM time s...

Page 146: ...D0 023C XBUF15 1 Transmit buffer register for serializer 15 0x01D0 0280 RBUF0 2 Receive buffer register for serializer 0 0x01D0 0284 RBUF1 2 Receive buffer register for serializer 1 0x01D0 0288 RBUF2...

Page 147: ...cASP0 ACLKRCTL CLKRM 1 PDIR ACLKR 1 ACLKR0 external input McASP0 ACLKRCTL CLKRM 0 PDIR ACLKR 0 ACLKR0 external output McASP0 ACLKRCTL CLKRM 0 PDIR ACLKR 1 2 P SYSCLK2 period 3 This timing is limited b...

Page 148: ...LKXCTL ASYNC 1 Receiver is clocked by its own ACLKR0 5 McASP0 ACLKXCTL ASYNC 0 Receiver is clocked by transmitter s ACLKX0 Table 6 53 Timing Requirements for McASP0 1 0V 1 2 NO 1 0V UNIT MIN MAX 1 tc...

Page 149: ...edge to AXR output valid ACLKR X int 1 6 1 8 ns ACLKR X ext input 2 13 5 2 15 ns ACLKR X ext output 2 13 5 2 15 ns 15 tdis ACLKX AXRHZ Disable time ACLKR X transmit edge to AXR high impedance followi...

Page 150: ...20C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas...

Page 151: ...1 A 151 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 20...

Page 152: ...0x01D1 100C RCR McBSP Receive Control Register 0x01D1 0010 0x01D1 1010 XCR McBSP Transmit Control Register 0x01D1 0014 0x01D1 1014 SRGR McBSP Sample Rate Generator register 0x01D1 0018 0x01D1 1018 MC...

Page 153: ...ic speed the maximum usable speed may be lower due to EDMA limitations and AC timing requirements 4 This parameter applies to the maximum McBSP frequency Operate serial clocks CLKR X in the reasonable...

Page 154: ...lower due to EDMA limitations and AC timing requirements 4 This parameter applies to the maximum McBSP frequency Operate serial clocks CLKR X in the reasonable range of 40 60 duty cycle Table 6 58 Ti...

Page 155: ...d the maximum limit see 4 above 7 Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2...

Page 156: ...ould be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit see 4 above 7 Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only...

Page 157: ...ow CLKR int 15 18 ns CLKR ext 5 5 6 th CKRL FRH Hold time external FSR high after CLKR low CLKR int 6 6 ns CLKR ext 3 3 7 tsu DRV CKRL Setup time DR valid before CLKR low CLKR int 15 18 ns CLKR ext 5...

Page 158: ...to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2 12P 8 Extra delay from FSX high to DX valid applies only to the first data bit of a de...

Page 159: ...mum limit see 4 above 7 Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2 12P 8 Extr...

Page 160: ...ments Incorporated A No 13 applies to the first data bit only when XDATDLY 0 Figure 6 34 McBSP Timing Table 6 65 Timing Requirements for McBSP0 FSR When GSYNC 1 see Figure 6 35 NO 1 3V 1 2V 1 1V 1 0V...

Page 161: ...OMI and two optional pins SPIx_SCS SPIx_ENA The optional SPIx_SCS Slave Chip Select pin is most useful to enable in slave mode when there are other slave devices on the same SPI port The device will o...

Page 162: ...Ix_ENA SPIx_ENA SPIx_SCS SPIx_SCS 162 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrica...

Page 163: ...0x01C4 1020 0x01F0 E020 SPIPC3 Pin Control Register 3 Pin Data Out 0x01C4 1024 0x01F0 E024 SPIPC4 Pin Control Register 4 Pin Data Set 0x01C4 1028 0x01F0 E028 SPIPC5 Pin Control Register 5 Pin Data Cle...

Page 164: ...initial edge on SPI0_CLK 3 Polarity 0 Phase 0 to SPI0_CLK rising 5 5 6 ns Polarity 0 Phase 1 to SPI0_CLK rising 0 5M 5 0 5M 5 0 5M 6 Polarity 1 Phase 0 to SPI0_CLK falling 5 5 6 Polarity 1 Phase 1 to...

Page 165: ...ge from master 3 4 Polarity 0 Phase 0 to SPI0_CLK rising 2P 2P 2P ns Polarity 0 Phase 1 to SPI0_CLK rising 2P 2P 2P Polarity 1 Phase 0 to SPI0_CLK falling 2P 2P 2P Polarity 1 Phase 1 to SPI0_CLK falli...

Page 166: ...ng 0 5M 3P 5 0 5M 3P 5 0 5M 3P 6 18 td SPC_ENA M Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer 5 Polarity 0 Phase 0 from SPI0_CLK...

Page 167: ...r all four master clocking modes 4 In the case where the master SPI is ready with new data before SPI0_ENA deassertion 5 Except for modes when SPIDAT1 CSHOLD is enabled and there is additional data to...

Page 168: ...P 2 0 5M 2P 3 23 td ENA_SPC M Delay from assertion of SPI0_ENA low to first SPI0_CLK edge 10 Polarity 0 Phase 0 to SPI0_CLK rising 3P 5 3P 5 3P 6 ns Polarity 0 Phase 1 to SPI0_CLK rising 0 5M 3P 5 0 5...

Page 169: ...SPI0_SCS to slave driving SPI0_SOMI valid P 17 5 P 20 P 27 ns 28 tdis SCSH_SOMI S Delay from master deasserting SPI0_SCS to slave 3 stating SPI0_SOMI P 17 5 P 20 P 27 ns 1 These parameters are in add...

Page 170: ...he SPIINT0 ENABLE_HIGHZ bit is programmed to 0 Otherwise it is tri stated If tri stated an external pullup resistor should be used to provide a valid level to the master This option is useful when tyi...

Page 171: ...CLK rising 0 5M 5 0 5M 5 0 5M 6 Polarity 1 Phase 0 to SPI1_CLK falling 5 5 6 Polarity 1 Phase 1 to SPI1_CLK falling 0 5M 5 0 5M 5 0 5M 6 5 td SPC_SIMO M Delay subsequent bits valid on SPI1_SIMO after...

Page 172: ...ge from master 3 4 Polarity 0 Phase 0 to SPI1_CLK rising 2P 2P 2P ns Polarity 0 Phase 1 to SPI1_CLK rising 2P 2P 2P Polarity 1 Phase 0 to SPI1_CLK falling 2P 2P 2P Polarity 1 Phase 1 to SPI1_CLK falli...

Page 173: ...P 5 P 5 P 6 Polarity 1 Phase 0 from SPI1_CLK rising 0 5M P 5 0 5M P 5 0 5M P 6 Polarity 1 Phase 1 from SPI1_CLK rising P 5 P 5 P 6 1 These parameters are in addition to the general timings for SPI mas...

Page 174: ...onal 1 SPI1 Master Timings 5 Pin Option 2 3 NO PARAMETER 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX MIN MAX MIN MAX 18 td SPC_ENA M Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure m...

Page 175: ..._CLK falling 0 5M 3P 5 0 5M 3P 5 0 5M 3P 6 1 These parameters are in addition to the general timings for SPI slave modes Table 6 77 2 P SYSCLK2 period M tc SPC M SPI master bit clock period 3 Figure s...

Page 176: ...rting SPI1_SCS to slave driving SPI1_SOMI valid P 15 P 17 P 19 ns 28 tdis SCSH_SOMI S Delay from master deasserting SPI1_SCS to slave 3 stating SPI1_SOMI P 15 P 17 P 19 ns 1 These parameters are in ad...

Page 177: ...if the SPIINT0 ENABLE_HIGHZ bit is programmed to 0 Otherwise it is tri stated If tri stated an external pullup resistor should be used to provide a valid level to the master This option is useful when...

Page 178: ...O n MI 0 MI 1 MI n 1 MI n 6 6 7 7 7 7 8 8 8 8 3 2 6 1 4 4 4 4 5 5 5 6 MASTER MODE POLARITY 0 PHASE 0 MASTER MODE POLARITY 0 PHASE 1 MASTER MODE POLARITY 1 PHASE 0 MASTER MODE POLARITY 1 PHASE 1 5 178...

Page 179: ...SO 1 SO n 1 SO n 14 14 15 15 15 15 16 16 16 16 11 10 14 9 12 12 12 12 13 13 13 13 14 SLAVE MODE POLARITY 0 PHASE 0 SLAVE MODE POLARITY 0 PHASE 1 SLAVE MODE POLARITY 1 PHASE 0 SLAVE MODE POLARITY 1 PH...

Page 180: ...MI 1 MI n 1 MI n 17 19 21 22 23 20 18 20 18 MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP DESEL A DESEL A 180 TMS320C674...

Page 181: ...28 25 25 27 29 SLAVE MODE 4 PIN WITH ENABLE SLAVE MODE 4 PIN WITH CHIP SELECT SLAVE MODE 5 PIN DESEL A DESEL A A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP 181 TMS320C6...

Page 182: ...egister I2CPDIN Pin Data In Register I2CPDOUT Pin Data Out Register I2CPDSET Pin Data Set Register I2CPDCLR Pin Data Clear Register Interrupt DMA Requests 182 TMS320C6748 SPRS590G JUNE 2009 REVISED JA...

Page 183: ...egister 0x01C2 2014 0x01E2 8014 ICCNT I2C Data Count Register 0x01C2 2018 0x01E2 8018 ICDRR I2C Data Receive Register 0x01C2 201C 0x01E2 801C ICSAR I2C Slave Address Register 0x01C2 2020 0x01E2 8020 I...

Page 184: ...e duration I2Cx_SDA high 4 7 1 3 s 9 tr SDA Rise time I2Cx_SDA 1000 20 0 1Cb 300 ns 10 tr SCL Rise time I2Cx_SCL 1000 20 0 1Cb 300 ns 11 tf SDA Fall time I2Cx_SDA 300 20 0 1Cb 300 ns 12 tf SCL Fall ti...

Page 185: ...d Start Stop I2Cx_SDA I2Cx_SCL 1 11 9 185 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Elect...

Page 186: ...ulation Modem control functions CTS RTS The UART registers are listed in Section 6 19 1 6 19 1 UART Peripheral Registers Description s Table 6 87 is the list of UART registers Table 6 87 UART Register...

Page 187: ...T0 the UART input clock is SYSCLK2 For UART1 or UART2 the UART input clock is ASYNC3 either PLL0_SYCLK2 or PLL1_SYSCLK2 3 E UART divisor x UART sampling rate The UART divisor is set through the UART d...

Page 188: ...ID Revision Register 0x01E0 0004 CTRLR Control Register 0x01E0 0008 STATR Status Register 0x01E0 000C EMUR Emulation Register 0x01E0 0010 MODE Mode Register 0x01E0 0014 AUTOREQ Autorequest Register 0x...

Page 189: ...OUNT Number of Bytes in Host Receive Endpoint FIFO Index register set to select Endpoints 1 4 0x01E0 041A HOST_TYPE0 Defines the speed of Endpoint 0 HOST_TXTYPE Sets the operating speed transaction pr...

Page 190: ...sed only when full speed or low speed device is connected via a USB2 0 high speed hub 0x01E0 048B TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint This is use...

Page 191: ...ssed through the associated Receive Endpoint 0x01E0 04A6 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint This is used only when full speed or low speed dev...

Page 192: ...e Endpoint peripheral mode HOST_RXCSR Control Status Register for Host Receive Endpoint host mode 0x01E0 0538 RXCOUNT Number of Bytes in Host Receive endpoint FIFO 0x01E0 053A HOST_TXTYPE Sets the ope...

Page 193: ...e Channel 3 Host Packet Configuration Register B 0x01E0 2000 DMA_SCHED_CTRL DMA Scheduler Control Register 0x01E0 2800 WORD 0 DMA Scheduler Table Word 0 0x01E0 2804 WORD 1 DMA Scheduler Table Word 1 0...

Page 194: ...trical Data Timing The USB PHY PLL can support input clock of the following frequencies 12 0 MHz 13 0 MHz 19 2 MHz 20 0 MHz 24 0 MHz 26 0 MHz 38 4 MHz 40 0 MHz or 48 0 MHz USB_REFCLKIN jitter toleranc...

Page 195: ...NTROLHEADED HC Head Control Register 1 0x01E2 5024 HCCONTROLCURRENTED HC Current Control Register 1 0x01E2 5028 HCBULKHEADED HC Head Bulk Register 1 0x01E2 502C HCBULKCURRENTED HC Current Bulk Registe...

Page 196: ...s Masked Register 0x01E2 3088 TXINTMASKSET Transmit Interrupt Mask Set Register 0x01E2 308C TXINTMASKCLEAR Transmit Interrupt Clear Register 0x01E2 3090 MACINVECTOR MAC Input Vector Register 0x01E2 30...

Page 197: ...Register 0x01E2 3200 0x01E2 32FC see Table 6 95 EMAC Statistics Registers 0x01E2 3500 MACADDRLO MAC Address Low Bytes Register Used in Receive Address Matching 0x01E2 3504 MACADDRHI MAC Address High...

Page 198: ...RS Receive CRC Errors Register Total number of frames received with CRC errors 0x01E2 3214 RXALIGNCODEERRORS Receive Alignment Code Errors Register Total number of frames received with alignment code...

Page 199: ...1 Miscellaneous Interrupt Enable Register 0x01E2 2030 C2RXTHRESHEN EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register 0x01E2 2034 C2RXEN EMAC Control Module Interrupt Co...

Page 200: ..._RXCLK see Figure 6 47 NO 1 3V 1 2V 1 1V 1 0V UNIT 10 Mbps 100 Mbps 10 Mbps MIN MAX MIN MAX MIN MAX 1 tc MII_RXCLK Cycle time MII_RXCLK 400 40 400 ns 2 tw MII_RXCLKH Pulse duration MII_RXCLK high 140...

Page 201: ...ceive 10 100 Mbit s 1 see Figure 6 49 NO 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX 1 tsu MRXD MII_RXCLKH Setup time receive selected signals valid before MII_RXCLK high 8 ns 2 th MII_RXCLKH MRXD Hold time rece...

Page 202: ...7 th REFCLK RXD Input Hold Time RXD Valid after RMII_MHZ_50_CLK High 2 ns 8 tsu CRSDV REFCLK Input Setup Time CRSDV Valid before RMII_MHZ_50_CLK High 4 ns 9 th REFCLK CRSDV Input Hold Time CRSDV Vali...

Page 203: ...essor Only one PHY may be connected at any given time 6 23 1 MDIO Register Description s Table 6 104 MDIO Register Memory Map BYTE ADDRESS ACRONYM REGISTER NAME 0x01E2 4000 REV Revision Identification...

Page 204: ...6 53 NO 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX MIN MAX 1 tc MDCLK Cycle time MDCLK 400 400 ns 2 tw MDCLK Pulse duration MDCLK high low 180 180 ns 3 tt MDCLK Transition time MDCLK 5 5 ns 4 tsu MDIO MDCLKH S...

Page 205: ...aximum frame rate is determined by the image size in combination with the pixel clock rate For details see SPRAB93 Table 6 107 lists the LCD Controller registers Table 6 107 LCD Controller Registers B...

Page 206: ...ver Recommended Operating Conditions for LCD LIDD Mode NO PARAMETER 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX MIN MAX 4 td LCD_D_V Delay time LCD_MCLK high to LCD_D 15 0 valid write 0 7 0 9 ns 5 td LCD_D_I Del...

Page 207: ...13 10 11 Not Used LCD_D 7 0 14 17 16 Read Data 15 4 5 E0 E1 12 13 Data 7 0 Write Instruction 207 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Fo...

Page 208: ...1 15 CS_DELAY 5 4 5 6 7 6 7 8 9 12 13 Write Address Write Data 12 13 10 11 10 11 Data 15 0 208 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Fol...

Page 209: ...1 15 CS_DELAY 5 14 15 6 7 6 7 8 9 12 13 17 16 Write Address Read Data 10 11 12 13 Data 15 0 209 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Fo...

Page 210: ...15 CS_DELAY 14 15 6 7 6 7 8 9 12 13 17 16 14 17 16 15 12 13 Data 15 0 R_SU 0 31 Read Status 210 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Fol...

Page 211: ...W_HOLD 0 31 1 63 1 15 CS_DELAY 5 4 5 6 7 6 7 8 9 10 11 Write Address Write Data 10 11 211 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Li...

Page 212: ...63 1 15 CS_DELAY 5 14 15 6 7 6 7 8 9 12 13 17 16 Read Data 10 11 Data 15 0 Write Address 212 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folde...

Page 213: ...5 6 7 6 8 12 13 17 16 Read Status 14 17 16 Read Data 15 12 13 Data 15 0 7 9 R_SU 0 31 213 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Li...

Page 214: ...9 ns 9 td LCD_VSYNC_I Delay time LCD_PCLK low to LCD_VSYNC low 0 7 0 9 ns 10 td LCD_HSYNC_A Delay time LCD_PCLK high to LCD_HSYNC high 0 7 0 9 ns 11 td LCD_HSYNC_I Delay time LCD_PCLK high to LCD_HSY...

Page 215: ...ta Pixels From 1 to P Data Lines From 1 to L 1 215 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information...

Page 216: ...LCD_PCLK LCD_D 15 0 1 1 2 2 P 2 P 1 2 1 1 2 PLL 16 1 to 1024 HBP 1 to 256 Line 1 1 to 256 HFP 1 to 64 HSW PLL 16 1 to 1024 Line 2 Data LCD_AC_ENB_CS Enable 216 TMS320C6748 SPRS590G JUNE 2009 REVISED...

Page 217: ...JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated F...

Page 218: ...LCD_AC_ENB_CS LCD_D 7 0 passive mode 1 L 2 1 P 1 P L 2 L 1 1 10 11 8 6 4 4 5 5 1 2 3 1 2 3 VSW 1 VFP 0 VBP 0 218 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Fee...

Page 219: ..._D 7 0 passive mode 1 1 2 2 P 2 P 1 2 1 1 2 10 11 9 7 4 5 1 2 3 VSW 1 VFP 0 VBP 0 P 1 1 1 2 1 4 5 1 3 4 Line 2 for passive 219 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Doc...

Page 220: ...sters within the UHPI provide the data path between the external host interface and the processor resources A UHPI control register HPIC is available to the host and the CPU for various configuration...

Page 221: ...BE low 5 ns 2 th HSTBL SELV Hold time select signals 3 valid after UHPI_HSTROBE low 2 ns 3 tw HSTBL Pulse duration UHPI_HSTROBE active low 15 ns 4 tw HSTBH Pulse duration UHPI_HSTROBE inactive high be...

Page 222: ...First half word access of HPID Read without auto increment For HPI Read HRDY stays low ready for these HPI Read conditions Case 1 HPID read with auto increment and data is already in Read FIFO applie...

Page 223: ...First half word access of HPID Read without auto increment For HPI Read HRDY stays low ready for these HPI Read conditions Case 1 HPID read with auto increment and data is already in Read FIFO applies...

Page 224: ...auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur C UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2...

Page 225: ...SED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated A For correct op...

Page 226: ...auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur C UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2...

Page 227: ...JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated A For correct operat...

Page 228: ...maximize throughput and minimize CPU overhead during high speed data transmission All uPP transactions use the internal DMA to provide data to or retrieve data from the I O channels The DMA controlle...

Page 229: ...1 6020 UPISR uPP Interrupt Raw Status Register 0x01E1 6024 UPIER uPP Interrupt Enabled Status Register 0x01E1 6028 UPIES uPP Interrupt Enable Set Register 0x01E1 602C UPIEC uPP Interrupt Enable Clear...

Page 230: ...5 ns 7 th INCLKH ENV Hold time CHn_ENABLE valid after CHn_CLK high 0 8 0 8 0 8 ns 8 tsu DV INCLKH Setup time CHn_DATA XDATA valid before CHn_CLK high 4 5 5 6 5 ns 9 th INCLKH DV Hold time CHn_DATA XDA...

Page 231: ...1 Data3 Data4 2 CHx_WAIT Data5 Data6 1 Data7 Data8 Data9 3 5 4 7 6 9 8 231 TMS320C6748 www ti com SPRS590G JUNE 2009 REVISED JANUARY 2017 Submit Documentation Feedback Product Folder Links TMS320C6748...

Page 232: ...14 20 19 CHx_CLK CHx_START CHx_ENABLE CHx_DATA n 0 CHx_XDATA n 0 CHx_WAIT 232 TMS320C6748 SPRS590G JUNE 2009 REVISED JANUARY 2017 www ti com Submit Documentation Feedback Product Folder Links TMS320C...

Page 233: ...and Channel 1 Two 8 bit Standard Definition SD Video with embedded timing codes BT 656 Single 16 bit High Definition HD Video with embedded timing codes BT 1120 Single Raw Video 8 10 12 bit Up to 2 Vi...

Page 234: ...058 CH0_TVA_STRTADR Channel 0 Top Field vertical ancillary data buffer start address 0x01E1 705C CH0_BVA_STRTADR Channel 0 Bottom Field vertical ancillary data buffer start address 0x01E1 7060 CH0_SUB...

Page 235: ...1 70FC CH2_VSIZE Channel 2 vertical image size 0x01E1 7100 CH2_THA_STRTPOS Channel 2 Top Field horizontal ancillary data insertion start position 0x01E1 7104 CH2_THA_SIZE Channel 2 Top Field horizonta...

Page 236: ...01E1 7184 CH3_THA_SIZE Channel 3 Top Field horizontal ancillary data size 0x01E1 7188 CH3_BHA_STRTPOS Channel 3 Bottom Field horizontal ancillary data insertion start position 0x01E1 718C CH3_BHA_SIZE...

Page 237: ...lectrical Data Timing 1 C VP_CLKINx period in ns Table 6 119 Timing Requirements for VPIF VP_CLKINx Inputs 1 see Figure 6 75 NO 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX MIN MAX MIN MAX 1 tc VKI Cycle time VP_...

Page 238: ...time VP_DINx valid after VP_CLKIN0 1 high 0 5 0 0 0 ns 1 C VP_CLKO2 3 period in ns Figure 6 76 VPIF Channels 0 1 Video Capture Data and Control Input Timing Table 6 121 Switching Characteristics Over...

Page 239: ...ween position sensor triggers Period and duty cycle measurements of pulse train signals Decoding current or voltage amplitude derived from duty cycle encoded current voltage sensors The ECAP module de...

Page 240: ...ut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR PRD CTR_OVF 4 PWM compare logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM mode Delta mod...

Page 241: ...6028 0x01F0 7028 0x01F0 8028 ECCTL1 Capture Control Register 1 0x01F0 602A 0x01F0 702A 0x01F0 802A ECCTL2 Capture Control Register 2 0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT Capture Interrupt Enable...

Page 242: ...17 www ti com Submit Documentation Feedback Product Folder Links TMS320C6748 Peripheral Information and Electrical Specifications Copyright 2009 2017 Texas Instruments Incorporated 6 29 Enhanced High...

Page 243: ...C CMPB active 16 CTR CMPB CMPB shadow 16 CMPAHR 8 EPWMA EPWMB Dead band DB PC chopper PWM zone TZ Trip CTR ZERO EPWMxA EPWMxB EPWMxTZINT TZ HiRes PWM HRPWM CTR PRD CTR ZERO CTR CMPB CTR CMPA CTR_Dir E...

Page 244: ...fier Control Register for Output A eHRPWMxA 0x01F0 0018 0x01F0 2018 AQCTLB No Action Qualifier Control Register for Output B eHRPWMxB 0x01F0 001A 0x01F0 201A AQSFRC No Action Qualifier Software Force...

Page 245: ...S 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX tw SYNCIN Sync input pulse width Asynchronous 2tc SCO cycles Synchronous 2tc SCO cycles Table 6 127 Switching Characteristics Over Recommended Operating Conditions f...

Page 246: ...9 2017 Texas Instruments Incorporated 6 29 2 Trip Zone Input Timing A PWM refers to all the PWM pins in the device The state of the PWM pins after TZ is taken high depends on the PWM recovery software...

Page 247: ...mer Counter Register 34 0x01C2 0018 0x01C2 1018 0x01F0 C018 0x01F0 D018 PRD12 Timer Period Register 12 0x01C2 001C 0x01C2 101C 0x01F0 C01C 0x01F0 D01C PRD34 Timer Period Register 34 0x01C2 0020 0x01C2...

Page 248: ...n input signals Table 6 130 Timing Requirements for Timer Input 1 2 see Figure 6 82 NO 1 3V 1 2V 1 1V 1 0V UNIT MIN MAX 1 tc TM64Px_IN12 Cycle time TM64Px_IN12 4P ns 2 tw TINPH Pulse duration TM64Px_I...

Page 249: ...rites so that updates do not interfere with the accuracy of the time and date Alarms are available to interrupt the CPU at a particular time or at periodic time intervals such as once per minute or on...

Page 250: ...red to preserve the current time and calendar information Even if the RTC is not used it must remain powered when the rest of the device is powered The source for the RTC reference clock may be provid...

Page 251: ...f the Week Register 0x01C2 3020 ALARMSECOND Alarm Seconds Register 0x01C2 3024 ALARMMINUTE Alarm Minutes Register 0x01C2 3028 ALARMHOUR Alarm Hours Register 0x01C2 302C ALARMDAY Alarm Days Register 0x...

Page 252: ...upt requests within each bank are combined logical or to create eight unique bank level interrupt requests The bank level interrupt service routine may poll the INTSTATx register for its bank to deter...

Page 253: ...E2 6038 DIR23 GPIO Banks 2 and 3 Direction Register 0x01E2 603C OUT_DATA23 GPIO Banks 2 and 3 Output Data Register 0x01E2 6040 SET_DATA23 GPIO Banks 2 and 3 Set Data Register 0x01E2 6044 CLR_DATA23 GP...

Page 254: ...RIS_TRIG67 GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register 0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks 6 and 7 Set Falling Edge Interrupt Register 0x01E2 60A8 CLR_FAL_TRIG67 GPIO Banks 6 and 7 Clear...

Page 255: ...used as a maximum performance specification Actual performance of back to back accesses of the GPIO is dependent upon internal bus activity 2 C SYSCLK4 period in ns Table 6 135 Switching Characteristi...

Page 256: ...aps are implemented inside the PRUSS and are local to the components of the PRUSS Table 6 137 Programmable Real Time Unit Subsystem PRUSS Local Instruction Space Memory Map BYTE ADDRESS PRU0 PRU1 0x00...

Page 257: ...er 0x01C3 7008 0x01C3 7808 WAKEUP PRU Wakeup Enable Register 0x01C3 700C 0x01C3 780C CYCLCNT PRU Cycle Count 0x01C3 7010 0x01C3 7810 STALLCNT PRU Stall Count 0x01C3 7020 0x01C3 7820 CONTABBLKIDX0 PRU...

Page 258: ...errupt Enable Set Register 0 0x01C3 4304 ENABLESET1 System Interrupt Enable Set Register 1 0x01C3 4380 ENABLECLR0 System Interrupt Enable Clear Register 0 0x01C3 4384 ENABLECLR1 System Interrupt Enabl...

Page 259: ...fy targeted memory level s during memory accesses HSRTDX High Speed Real Time Data eXchange Advanced System Control Subsystem reset via debug Peripheral notification of debug events Cache coherent deb...

Page 260: ...l test and debug logic in the device to be reset along with the IEEE 1149 1 interface TCK I Test Clock This is the test clock used to drive an IEEE 1149 1 TAP state machine and logic TMS I Test Mode S...

Page 261: ...ents actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST When using this type of JTAG controller assert TRST to i...

Page 262: ...lid before TCK high 4 4 4 ns 5 th TCLKH TDIV Hold time TDI TMS TRST valid after TCK high 4 6 8 ns Table 6 148 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port see Fig...

Page 263: ...ice that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality a...

Page 264: ...i com uniform resource locator URL For information on pricing and availability contact the nearest TI field sales office or authorized distributor 7 3 Documentation Support To receive notification of...

Page 265: ...ems with fellow engineers TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledg...

Page 266: ...ssumed PCB with 2oz 70um top and bottom copper thickness and 1 5oz 50um inner copper thickness 2 m s meters per second 8 Mechanical Packaging and Orderable Information This section describes the order...

Page 267: ...ttom copper thickness and 1 5oz 50um inner copper thickness 2 m s meters per second 8 2 Thermal Data for ZWT Package The following table shows the thermal resistance characteristics for the PBGA ZWT m...

Page 268: ...TMS320 C6748BZCE A375 TMS320C6748BZCEA3E OBSOLETE NFBGA ZCE 361 TBD Call TI Call TI 40 to 105 TMS320 C6748BZCE E A375 TMS320C6748BZCED4 OBSOLETE NFBGA ZCE 361 TBD Call TI Call TI 40 to 90 TMS320 C6748...

Page 269: ...l 3 260C 168 HR 40 to 105 TMS320 C6748EZCE E A375 TMS320C6748EZCED4 ACTIVE NFBGA ZCE 361 160 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 TMS320 C6748EZCE D450 TMS320C6748EZWT3 ACTIVE NFBGA...

Page 270: ...nts Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperat...

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Page 273: ...duct s identified in such TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY...

Page 274: ...ZCEA3 TMS320C6748BZCED4 TMS320C6748BZWT3 TMS320C6748BZWT4 TMS320C6748BZWTA3 TMS320C6748BZWTD4 TMS320C6748BZCEA3E TMS320C6748BZCED4E TMS320C6748BZWTA3E TMS320C6748BZWTD4E TMS320C6748EZWTD4E TMS320C6748...

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