Texas Instruments MSP430F67691, Manual

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Description Changing the SELM/SELS/SELA bits in the UCSCTL4 register will correctly configure the
respective clock to use the intended clock source but might also erroneously set XT1/XT2
fault flag if the crystals are not present at XT1/XT2 or not configured in the application
firmware. If the NMI interrupt for the OFIFG is enabled, an unintentional NMI interrupt will
be triggered and needs to be handled.
Note
The XT1/XT2 fault flag can be set regardless of which SELM/SELS/SELA bit
combinations are being changed.
Workaround Clear all the fault flags in UCSCTL7 register once after changing any of the SELM/SELS/
SELA bits in the UCSCTL4 register.
If OFIFG-NMI is enabled during clock switching, disable OFIFG-NMI interrupt during
changing the SELM/SELS/SELA bits in the UCSCTL4 register to prevent unintended NMI.
Alternatively it can be handled accordingly (clear falsely set fault flags) in the Interrupt
Service Routine to ensure proper OFIFG clearing.
USCI36
USCI Module
Category Functional
Function UCLKI not usable in I2C master mode
Description When EUSCIB is configured as I2C Master with the external UCLKI as clock source, the
UCLKI signal is not available and cannot be used to source I2C clock.
Workaround Use LFXTCLK via ACLK or HFXTCLK via SMCLK as clock source (BRCLK) for I2C in
master mode with external clock source.
USCI37
USCI Module
Category Functional
Function Reading RXBUF during an active I2C communication might result in unintended bus
stalls.
Description The falling edge of SCL bus line is used to set an internal RXBUF-written flag register,
which is used to detect a potential RXBUF overflow. If this flag is cleared with a read
access from the RXBUF register during a falling edge of SCL, the clear condition might be
missed. This could result in an I2C bus stall at the next received byte.
Workaround (1) Execute two consecutive reads of RXBUF, if t
SCL
> 4 x t
MCLK
.
or
(2) Provoke an I2C bus stall before reading RXBUF. A bus stall can be verified by
checking if the clock line low status indicator bit UCSCLLOW is set for at least three USCI
bit clock cycles i.e. 3 x t
BitClock
.
USCI41
USCI Module
Category Functional
Function UCBUSY bit of eUSCIA module might not work reliable when device is in SPI mode.
Description When eUSCIA is configured in SPI mode, the UCBUSY bit might get stuck to 1 or start
toggling after transmission is completed. This happens in all four combinations of Clock
www.ti.com Advisory Descriptions
SLAZ509AC – JANUARY 2013 – REVISED MAY 2021
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MSP430F67691 Microcontroller 23
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