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PRODUCTPREVIEW

MSP430F663x

www.ti.com

SLAS566 – OCTOBER 2009

Table 42. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 0

UCA1CTL0

00h

USCI control 1

UCA1CTL1

01h

USCI baud rate 0

UCA1BR0

06h

USCI baud rate 1

UCA1BR1

07h

USCI modulation control

UCA1MCTL

08h

USCI status

UCA1STAT

0Ah

USCI receive buffer

UCA1RXBUF

0Ch

USCI transmit buffer

UCA1TXBUF

0Eh

USCI LIN control

UCA1ABCTL

10h

USCI IrDA transmit control

UCA1IRTCTL

12h

USCI IrDA receive control

UCA1IRRCTL

13h

USCI interrupt enable

UCA1IE

1Ch

USCI interrupt flags

UCA1IFG

1Dh

USCI interrupt vector word

UCA1IV

1Eh

Table 43. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 0

UCB1CTL0

00h

USCI synchronous control 1

UCB1CTL1

01h

USCI synchronous bit rate 0

UCB1BR0

06h

USCI synchronous bit rate 1

UCB1BR1

07h

USCI I2C interrupt enable

UCB1I2CIE

08h

USCI synchronous status

UCB1STAT

0Ah

USCI synchronous receive buffer

UCB1RXBUF

0Ch

USCI synchronous transmit buffer

UCB1TXBUF

0Eh

USCI I2C own address

UCB1I2COA

10h

USCI I2C slave address

UCB1I2CSA

12h

USCI interrupt enable

UCB1IE

1Ch

USCI interrupt flags

UCB1IFG

1Dh

USCI interrupt vector word

UCB1IV

1Eh

Table 44. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Control register 0

ADC12CTL0

00h

Control register 1

ADC12CTL1

02h

Control register 2

ADC12CTL2

04h

Interrupt-flag register

ADC12IFG

0Ah

Interrupt-enable register

ADC12IE

0Ch

Interrupt-vector-word register

ADC12IV

0Eh

ADC memory-control register 0

ADC12MCTL0

10h

ADC memory-control register 1

ADC12MCTL1

11h

ADC memory-control register 2

ADC12MCTL2

12h

ADC memory-control register 3

ADC12MCTL3

13h

ADC memory-control register 4

ADC12MCTL4

14h

ADC memory-control register 5

ADC12MCTL5

15h

ADC memory-control register 6

ADC12MCTL6

16h

ADC memory-control register 7

ADC12MCTL7

17h

Copyright © 2009, Texas Instruments Incorporated

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Summary of Contents for MSP430F663x

Page 1: ...equency Internal Clock With Synchronization Source VLO Comparator Low Frequency Trimmed Internal Reference Integrated LCD Driver With Contrast Control Source REFO for up to 160 Segments 32 kHz Crystals XT1 Hardware Multiplier Supporting 32 Bit High Frequency Crystals Up to 32 MHz Operations XT2 Flash Memory 16 Bit Timer TA0 Timer_A With Five Serial Onboard Programming No External Capture Compare R...

Page 2: ... 16 2 5 3 3 7 2 2 2 12 74 4 int 113 ZQW 12 ext 100 PZ MSP430F6637 4 192 16 2 5 3 3 7 2 2 2 12 74 4 int 113 ZQW 12 ext 100 PZ MSP430F6636 4 128 16 2 5 3 3 7 2 2 2 12 74 4 int 113 ZQW 12 ext 100 PZ MSP430F6635 4 256 16 2 5 3 3 7 2 2 12 74 4 int 113 ZQW 12 ext 100 PZ MSP430F6634 4 192 16 2 5 3 3 7 2 2 12 74 4 int 113 ZQW 12 ext 100 PZ MSP430F6633 4 128 16 2 5 3 3 7 2 2 12 74 4 int 113 ZQW 100 PZ MSP4...

Page 3: ...MSP430F6633IPZ 3 MSP430F6633IZQW 3 MSP430F6632IPZ 3 MSP430F6632IZQW 3 MSP430F6631IPZ 3 MSP430F6631IZQW 3 MSP430F6630IPZ 3 MSP430F6630IZQW 3 1 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI web site at www ti com 2 Package drawings standard packing quantities thermal data symbolization and PCB design guidelines are ava...

Page 4: ...fied Clock System 256KB 192KB 128KB Flash 16KB RAM 2KB RAM USB Buffer 8B Backup RAM MCLK ACLK SMCLK I O Ports P1 P2 2 8 I Os Interrupt Capability PA 1 16 I Os CPUXV2 and Working Registers EEM L 8 2 XIN XOUT JTAG Interface Port PJ SBW PA PB PC PD DMA 6 Channel XT2IN XT OUT 2 Power Management LDO SVM Brownout SVS SYS Watchdog P2 Port Mapping Controller I O Ports P3 P4 2 8 I Os Interrupt Capability P...

Page 5: ... PD 1 14 I Os 1 8 I Os I O Ports P9 1 8 I Os PE 1 8 I Os MPY32 TA0 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers TB0 Timer_B 7 CC Registers CRC16 USCI0 1 Ax UART IrDA SPI Bx SPI I2C DVCC DVSS AVCC AVSS P1 x P2 x P3 x P4 x P5 x P6 x P7 x P8 x P9 x RST NMI REF Reference 1 5V 2 0V 2 5V LCD_B 160 Segments USB Full speed Comp_B EDI Enhanced Data Integrity PJ x RTC_B Battery Back...

Page 6: ...3 TCK PJ 2 TMS PJ 1 TDI TCLK PJ 0 TDO TEST SBWTCK P7 3 XT2OUT P7 2 XT2IN VBUS VUSB PU 1 DM PUR PU 0 DP VSSU V18 AVSS3 P1 3 TA0 2 S36 P1 4 TA0 3 S35 AVSS2 P5 6 ADC12CLK DMAE0 P5 4 COM2 S41 P5 5 COM3 S40 P1 0 TA0CLK ACLK S39 P3 0 TA1CLK CBOUT S31 P3 1 TA1 0 S30 P3 2 TA1 1 S29 P1 6 TA0 1 S33 P1 7 TA0 2 S32 P1 1 TA0 0 S38 P1 2 TA0 1 S37 P1 5 TA0 4 S34 P3 3 TA1 2 S28 P3 4 TA2CLK SMCLK S27 P3 5 TA2 0 S2...

Page 7: ... TMS PJ 1 TDI TCLK PJ 0 TDO TEST SBWTCK P7 3 XT2OUT P7 2 XT2IN VBUS VUSB PU 1 DM PUR PU 0 DP VSSU V18 AVSS3 P1 3 TA0 2 S36 P1 4 TA0 3 S35 AVSS2 P5 6 ADC12CLK DMAE0 P5 4 COM2 S41 P5 5 COM3 S40 P1 0 TA0CLK ACLK S39 P3 0 TA1CLK CBOUT S31 P3 1 TA1 0 S30 P3 2 TA1 1 S29 P1 6 TA0 1 S33 P1 7 TA0 2 S32 P1 1 TA0 0 S38 P1 2 TA0 1 S37 P1 5 TA0 4 S34 P3 3 TA1 2 S28 P3 4 TA2CLK SMCLK S27 P3 5 TA2 0 S26 P3 6 TA2...

Page 8: ...LK PJ 0 TDO TEST SBWTCK P7 3 XT2OUT P7 2 XT2IN VBUS VUSB PU 1 DM PUR PU 0 DP VSSU V18 AVSS3 P1 3 TA0 2 S36 P1 4 TA0 3 S35 AVSS2 P5 6 DMAE0 P5 4 COM2 S41 P5 5 COM3 S40 P1 0 TA0CLK ACLK S39 P3 0 TA1CLK CBOUT S31 P3 1 TA1 0 S30 P3 2 TA1 1 S29 P1 6 TA0 1 S33 P1 7 TA0 2 S32 P1 1 TA0 0 S38 P1 2 TA0 1 S37 P1 5 TA0 4 S34 P3 3 TA1 2 S28 P3 4 TA2CLK SMCLK S27 P3 5 TA2 0 S26 P3 6 TA2 1 S25 P3 7 TA2 2 S24 P4 ...

Page 9: ...J11 J12 H1 H2 H4 H5 H6 H7 H8 H9 H11 H12 K1 K2 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12 M4 ZQW PACKAGE TOP VIEW MSP430F663x www ti com SLAS566 OCTOBER 2009 Pin Designation MSP430F6638IZQW MSP430F6637IZQW MSP430F6636IZQW MSP430F6635IZQW MSP430F6634IZQW MSP430F6633IZQW MSP430F6632IZQW MSP430F6631IZQW MSP430F6630IZQW Copyright 2009 Texas Instruments Incorporat...

Page 10: ... external reference voltage to the ADC General purpose digital I O P5 1 VREF VeREF 10 E4 I O Negative terminal for the ADC s reference voltage for both sources the internal reference voltage or an external applied reference voltage E1 AVCC1 11 Analog power supply E2 AVSS1 12 F2 Analog ground supply XIN 13 F1 I Input terminal for crystal oscillator XT1 XOUT 14 G1 O Output terminal of crystal oscill...

Page 11: ...er TA0 clock signal TACLK input P1 0 TA0CLK ACLK S39 34 L5 I O ACLK output divided by 1 2 4 or 8 LCD segment output S39 General purpose digital I O with port interrupt Timer TA0 CCR0 capture CCI0A input compare Out0 output P1 1 TA0 0 S38 35 M5 I O BSL transmit output LCD segment output S38 General purpose digital I O with port interrupt Timer TA0 CCR1 capture CCI1A input compare Out1 output P1 2 T...

Page 12: ...igital I O with port interrupt P4 1 TB0 1 S22 51 M11 I O Timer TB0 capture CCR1 CCI1A CCI1B input compare Out1 output LCD segment output S22 General purpose digital I O with port interrupt P4 2 TB0 2 S21 52 L10 I O Timer TB0 capture CCR2 CCI2A CCI2B input compare Out2 output LCD segment output S21 General purpose digital I O with port interrupt P4 3 TB0 3 S20 53 M12 I O Timer TB0 capture CCR3 CCI3...

Page 13: ...al I O P9 3 S4 71 D11 I O LCD segment output S4 General purpose digital I O P9 4 S3 72 E9 I O LCD segment output S3 General purpose digital I O P9 5 S2 73 C12 I O LCD segment output S2 General purpose digital I O P9 6 S1 74 C11 I O LCD segment output S1 General purpose digital I O P9 7 S0 75 D9 I O LCD segment output S0 B11 VSSU 76 and USB PHY ground supply B12 General purpose digital I O controll...

Page 14: ...interrupt input Spy bi wire data input output General purpose digital I O P6 0 CB0 A0 97 B4 I O Comparator_B input CB0 Analog input A0 ADC not available on 6632 6631 6630 devices General purpose digital I O P6 1 CB1 A1 98 B3 I O Comparator_B input CB1 Analog input A1 ADC not available on 6632 6631 6630 devices General purpose digital I O P6 2 CB2 A2 99 A2 I O Comparator_B input CB2 Analog input A2...

Page 15: ... and constant generator respectively The remaining registers are general purpose registers Peripherals are connected to the CPU using data address and control buses and can be handled with all instructions Instruction Set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range Each instructio...

Page 16: ...led FLL loop control is disabled ACLK and SMCLK remain active MCLK is disabled Low power mode 2 LPM2 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DCO s dc generator remains enabled ACLK remains active Low power mode 3 LPM3 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DCO s dc generator is disabled ACLK remains active Low power mode 4 LPM4 CPU is disabled ACLK is d...

Page 17: ...R1 CCIFG1 to TA0CCR4 CCIFG4 Timer TA0 Maskable 0FFE8h 52 TA0IFG TA0IV 1 3 USB_UBM USB interrupts USBIV 1 3 Maskable 0FFE6h 51 DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA Maskable 0FFE4h 50 DMA4IFG DMA5IFG DMAIV 1 3 Timer TA1 TA1CCR0 CCIFG0 3 Maskable 0FFE2h 49 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2 Timer TA1 Maskable 0FFE0h 48 TA1IFG TA1IV 1 3 I O Port P1 P1IFG 0 to P1IFG 7 P1IV 1 3 Maskable 0FFDEh 47 USCI_A1 R...

Page 18: ...00h Sector 3 4 KB 4 KB 4 KB 0063FFh 005400h 0063FFh 005400h 0063FFh 005400h Sector 2 4 KB 4 KB 4 KB 0053FFh 004400h 0053FFh 004400h 0053FFh 004400h RAM Sector 1 4 KB 4 KB 4 KB 0043FFh 003400h 0043FFh 003400h 0043FFh 003400h Sector 0 4 KB 4 KB 4 KB 0033FFh 002400h 0033FFh 002400h 0033FFh 002400h Size 2KB 2KB 2KB USB RAM 2 RAM 0023FFh 001C00h 0023FFh 001C00h 0023FFh 001C00h Info A 128 B 128 B 128 B ...

Page 19: ...P430 flash memory controller The main purpose of the EDI function is gaining higher reliability of flash content and overall system integrity in harsh environments and application areas requiring this feature The additional level of security is reached by caluclating more dimensional checksums The on chip EDI support software allows easily to use the different EDI features The implementation cover...

Page 20: ... Table 7 Port Mapping Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS PM_CBOUT Comparator_B output 1 PM_TB0CLK Timer TB0 clock input PM_ADC12CLK ADC12CLK 2 PM_DMAE0 DMAE0 Input PM_SVMOUT SVM output 3 Timer TB0 high impedance input PM_TB0OUTH TB0OUTH 4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0 TB0 0 compare output Out0 5 PM_TB0...

Page 21: ... output USCI_A0 SPI slave P2 4 P2MAP4 SIMO in master out direction controlled by USCI PM_UCA0RXD PM_UCA0 USCI_A0 UART RXD direction controlled by USCI input USCI_A0 SPI slave P2 5 P2MAP5 SOMI out master in direction controlled by USCI P2 6 P2MAP6 R03 PM_NONE DVSS P2 7 P2MAP7 LCDREF R1 PM_NONE DVSS 3 Oscillator and System Clock The clock system in the MSP430F663x family of devices is supported by t...

Page 22: ...ration hardware The implementation on this device supports operation in LPM5 mode and operation from a backup supply Watchdog Timer WDT_A The primary function of the watchdog timer WDT_A module is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the modul...

Page 23: ...MI VMAIFG 019Ch 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh VLRLIFG 10h VLRHIFG 12h Reserved 14h to 1Eh Lowest No interrupt pending 00h NMIFG 02h Highest OFIFG 04h SYSUNIV User NMI 019Ah ACCVIFG 06h BUSIFG 08h Reserved 0Ah to 1Eh Lowest No interrupt pending 00h USB wait state timeout 02h Highest SYSBERRIV Bus Error EDI Error Cache hit XHIT 0198h 04h EDI Parity Error PERR 06h Reserved 08h to 1Eh Lowest Copyrigh...

Page 24: ...ibed in Table 10 Table 10 DMA Trigger Assignments Channel Trigger 0 1 2 3 4 5 0 DMAREQ 1 TA0CCR0 CCIFG 2 TA0CCR2 CCIFG 3 TA1CCR0 CCIFG 4 TA1CCR2 CCIFG 5 TA2CCR0 CCIFG 6 TA2CCR2 CCIFG 7 TBCCR0 CCIFG 8 TBCCR2 CCIFG 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 UCA0RXIFG 17 UCA0TXIFG 18 UCB0RXIFG 19 UCB0TXIFG 20 UCA1RXIFG 21 UCA1TXIFG 22 UCB1RXIFG 23 UCB1TXIFG ...

Page 25: ...e generated from the counter on overflow conditions and from each of the capture compare registers Table 11 Timer TA0 Signal Connections INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 34 P1 0 L5 P1 0 TA0CLK TACLK ACLK ACLK Timer NA NA SMCLK SMCLK 34 P1 0 L5 P1 0 TA0CLK TACLK 35 P1 1 M5 P1 1 TA0 0 CCI0A...

Page 26: ...LE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 42 P3 0 L7 P3 0 TA1CLK TACLK ACLK ACLK Timer NA NA SMCLK SMCLK 42 P3 0 L7 P3 0 TA1CLK TACLK 43 P3 1 H7 P3 1 TA1 0 CCI0A 43 P3 1 H7 P3 1 DVSS CCI0B CCR0 TA0 TA1 0 DVSS GND DVCC VCC 44 P3 2 M8 P3 2 TA1 1 CCI1A 44 P3 2 M8 P3 2 DAC12_A CBOUT CCI1B 1 DAC12_0 DAC12_1 internal CCR1 TA1 TA1 1 inter...

Page 27: ...tions INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 46 P3 4 J8 P3 4 TA2CLK TACLK ACLK ACLK Timer NA NA SMCLK SMCLK 46 P3 4 J8 P3 4 TA2CLK TACLK 47 P3 5 M9 P3 5 TA2 0 CCI0A 47 P3 5 M9 P3 5 DVSS CCI0B CCR0 TA0 TA2 0 DVSS GND DVCC VCC 48 P3 6 L9 P3 6 TA2 1 CCI1A 48 P3 6 L9 P3 6 CBOUT CCI1B internal CCR1 ...

Page 28: ... P4 1 TB0 1 CCI1A 51 P4 1 M11 P4 1 P2MAPx 1 P2MAPx 1 TB0 1 CCI1B P2MAPx 1 P2MAPx 1 CCR1 TB1 TB0 1 ADC12 internal 2 DVSS GND ADC12SHSx 3 DVCC VCC 52 P4 2 L10 P4 2 TB0 2 CCI2A 52 P4 2 L10 P4 2 P2MAPx 1 P2MAPx 1 TB0 2 CCI2B P2MAPx 1 P2MAPx 1 DAC12_A 3 CCR2 TB2 TB0 2 DVSS GND DAC12_0 DAC12_1 internal DVCC VCC 53 P4 3 M12 P4 3 TB0 3 CCI3A 53 P4 3 M12 P4 3 P2MAPx 1 P2MAPx 1 TB0 3 CCI3B P2MAPx 1 P2MAPx 1...

Page 29: ...tion Common and segment signals are generated as defined by the mode Static 2 mux 3 mux and 4 mux LCDs are supported The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump It is possible to control the level of the LCD voltage and thus contrast by software The module also provides an automatic blinking capability for individual segments USB Universal...

Page 30: ...3C0h 000h 02Eh Timer TA2 refer to Table 35 0400h 000h 02Eh Battery Backup refer to Table 36 0480h 000h 01Fh RTC_B refer to Table 37 04A0h 000h 01Fh 32 bit Hardware Multiplier refer to Table 38 04C0h 000h 02Fh DMA General Control refer to Table 39 0500h 000h 00Fh DMA Channel 0 refer to Table 39 0510h 000h 00Ah DMA Channel 1 refer to Table 39 0520h 000h 00Ah DMA Channel 2 refer to Table 39 0530h 000...

Page 31: ... Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 19 CRC16 Registers Base Address 0150h REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC result CRC16INIRES 04h Table 20 RAM Control Registers Base Address 0158h REGISTER DESCRIPTION REGISTER OFFSET RAM control 0 RCCTL0 00h Table 21 Watchdog Registers Base Address 015Ch REGISTER DESCRIPTION REGISTER OFFSET Watchdog timer c...

Page 32: ...gister PMAPPWD 00h Port mapping control register PMAPCTL 02h Port P2 0 mapping register P2MAP0 00h Port P2 1 mapping register P2MAP1 01h Port P2 2 mapping register P2MAP2 02h Port P2 3 mapping register P2MAP3 03h Port P2 4 mapping register P2MAP4 04h Port P2 5 mapping register P2MAP5 05h Port P2 6 mapping register P2MAP6 06h Port P2 7 mapping register P2MAP7 07h Table 26 Port P1 P2 Registers Base ...

Page 33: ...3IE 1Ah Port P3 interrupt flag P3IFG 1Ch Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup pulldown enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh Port P4 interrupt vector word P4IV 1Eh Port P4 interrupt edge select P4IES 19h Port P4 interrupt enable P4IE 1Bh Port P4 interrupt flag P4IFG 1Dh Table 28 Port P5 P6 Registers Base A...

Page 34: ...9 selection P9SEL 0Ah Table 31 Port J Registers Base Address 0320h REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup pulldown enable PJREN 06h Port PJ drive strength PJDS 08h Table 32 TA0 Registers Base Address 0340h REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture compare control 0 TA0CCTL0 02h Captur...

Page 35: ...0CCTL4 0Ah Capture compare control 5 TB0CCTL5 0Ch Capture compare control 6 TB0CCTL6 0Eh TB0 register TB0R 10h Capture compare register 0 TB0CCR0 12h Capture compare register 1 TB0CCR1 14h Capture compare register 2 TB0CCR2 16h Capture compare register 3 TB0CCR3 18h Capture compare register 4 TB0CCR4 1Ah Capture compare register 5 TB0CCR5 1Ch Capture compare register 6 TB0CCR6 1Eh TB0 expansion re...

Page 36: ...R 12h RTC day of week RTCDOW 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary to BCD conversion register BIN2BCD 1Ch BCD to binary conversion register BCD2BIN 1Eh Table 38 32 bit Hardware Multiplier Registers Base Address 04...

Page 37: ...06h DMA General Control DMA module control 4 DMACTL4 08h DMA General Control DMA interrupt vector DMAIV 0Ah DMA Channel 0 control DMA0CTL 00h DMA Channel 0 source address low DMA0SAL 02h DMA Channel 0 source address high DMA0SAH 04h DMA Channel 0 destination address low DMA0DAL 06h DMA Channel 0 destination address high DMA0DAH 08h DMA Channel 0 transfer size DMA0SZ 0Ah DMA Channel 1 control DMA1C...

Page 38: ...l 1 UCA0CTL1 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt...

Page 39: ...UCB1I2CIE 08h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh Table 44 ADC12_A Registers Base Address 0700h REGISTER DESCRIPTION REGISTER OFFS...

Page 40: ...emory 13 ADC12MEM13 3Ah Conversion memory 14 ADC12MEM14 3Ch Conversion memory 15 ADC12MEM15 3Eh Table 45 DAC12_A Registers Base Address 0780h REGISTER DESCRIPTION REGISTER OFFSET DAC12_A channel 0 control register 0 DAC12_0CTL0 00h DAC12_A channel 0 control register 1 DAC12_0CTL1 02h DAC12_A channel 0 data register DAC12_0DAT 04h DAC12_A channel 0 calibration control register DAC12_0CALCTL 06h DAC...

Page 41: ...terrupt flags OEPIFG 11h USB interrupt vector USBIV 12h USB maintenance MAINT 16h Time stamp TSREG 18h USB frame number USBFN 1Ah USB control USBCTL 1Ch USB interrupt enables USBIE 1Dh USB interrupt flags USBIFG 1Eh Function address FUNADR 1Fh Table 49 LCD_B Registers Base Address 0A00h REGISTER DESCRIPTION REGISTER OFFSET LCD_B control register 0 LCDBCTL0 000h LCD_B control register 1 LCDBCTL1 00...

Page 42: ...R 2009 www ti com Table 49 LCD_B Registers Base Address 0A00h continued REGISTER DESCRIPTION REGISTER OFFSET LCD_B blinking memory 22 LCDBM22 055h 42 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated D R A F T O N L Y ...

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