Evaluating with the ADCPro Software
19
SBAU140A – December 2008 – Revised February 2016
Copyright © 2008–2016, Texas Instruments Incorporated
MSOP-8EVM and MSOP-8EVM-PDK
7.1.2
Clockstop Mode—Max SCLK
In this mode, SCLK frequency is also the highest possible serial clock frequency for the data converter
under test. The sampling frequency can be adjusted to any desired rate by entering a value in the
sampling rate window. The primary difference in this mode of operation is that there are 24 cycles of the
serial clock applied to the ADC while the CS input is active. Delay time is added between CS to
accommodate the desired sampling rate.
Figure 15. Clockstop Mode—Max SCLK
7.1.3
Continuous Mode—Stretched SCLK
In this mode, SCLK frequency is calculated by the following equation: SCLK = sampling rate ×
cycles/sample. The number of clock cycles per sample period depend on the data converter under test
(for the ADS8326, this value is 24). Therefore, with the maximum sampling frequency, SCLK = 250kHz ×
24 = 6MHz. The number of SCLK cycles applied to the converter is fixed, and the period of the SCLK
automatically scales to reach the desired sampling rate for the given device.
Figure 16. Continuous Mode—Stretched SCLK
