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VIN nets are connected to bottom layer with multiple vias. This allows closer placement of the inductors, thus reducing SW node size
and EMI. Also snubber circuits are placed next to SW nets for EMI reduction. Multiple GND vias are used to provide solid ground around
the LP875761-Q1 device.

Figure 6-5. Top Layer

Board Layout

SNVU751 – OCTOBER 2020

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The LP875761Q1EVM Evaluation Module

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Copyright © 2020 Texas Instruments Incorporated

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Summary of Contents for LP875761-Q1

Page 1: ...29 8 Revision History 30 List of Figures Figure 2 1 LP875761Q1EVM 3 Figure 3 1 LP8757 Installer License Agreement 4 Figure 3 2 Features of LP8757 Installation 5 Figure 3 3 LP8757 Destination Folder 5 Figure 3 4 LP8757 Installation Complete 6 Figure 3 5 Evaluation Software Graphical User Interface GUI When Board Connected 6 Figure 3 6 Assert nRST 7 Figure 3 7 Read Registers Buttons 8 Figure 3 8 BUC...

Page 2: ...ble 4 2 I2C Compatible Bus Support 11 Table 4 3 Console Macros 18 Table 5 1 Bill of Materials for LP875761Q1EVM 19 1 Trademarks Microsoft Windows XP is a registered trademark of Microsoft Corporation All other trademarks are the property of their respective owners Trademarks www ti com 2 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instrume...

Page 3: ...5761Q1 Configurations PART NUMBER OUTPUT CONFIGURATION NUMBER OF OUTPUTS EVM NUMBER LP875761 Q1 4 phase 1 LP875761Q1EVM Figure 2 1 LP875761Q1EVM 3 Quick Setup Guide Many of the components on the LP875761Q1EVM are susceptible to damage by electrostatic discharge ESD Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM including the use of a grounded w...

Page 4: ...ler you want to install see Figure 3 2 4 Installer prompts to select Destination Folder see Figure 3 3 5 Press Install and the installation starts 6 Installer prompts when installation is complete see Figure 3 4 Open the LP8757 GUI Connect the EVM to the PC with the USB cable 1 With the power supply disconnected from the unit under test UUT open LP8757 exe located in the directory selected during ...

Page 5: ...s of LP8757 Installation Figure 3 3 LP8757 Destination Folder www ti com Quick Setup Guide SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 5 Copyright 2020 Texas Instruments Incorporated ...

Page 6: ... Figure 3 5 Evaluation Software Graphical User Interface GUI When Board Connected Quick Setup Guide www ti com 6 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 7: ...hat following steps are only an example Register values enable control mode and multiphase status may differ depending on the LP875761Q1EVM configuration 1 On Evaluation software GUI click on Assert NRST see Figure 3 6 2 Click on either of the two Read Registers buttons You should see ready message on green background next to the Read Registers button see Figure 3 7 3 Check that Buck0 is enabled c...

Page 8: ... 7 Read Registers Buttons Figure 3 8 BUCK0 Enabled Quick Setup Guide www ti com 8 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 9: ...Figure 3 9 Assert EN1 www ti com Quick Setup Guide SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 9 Copyright 2020 Texas Instruments Incorporated ...

Page 10: ...n Tab The Main tab see for example Figure 3 9 has the elemental controls for the EVM and provides a view to the chip status Starting from top the main controls are I2C mode or 4 Enable mode If this states I2C mode device is controlled with I2C When this states 4EN mode bucks are controlled with ENx pins Assert NRST This checkbox will assert high level to LP875761 Q1 NRST pin This pin enables the c...

Page 11: ...ely launch I2C writes to the chip register s If not checked the user can update the chip registers to correspond the configuration selected on the GUI by clicking Write Registers If Poll Status is selected the software sends a query to the LP875761 Q1 at a fixed interval in order to detect the status of the chip including operation mode multi phase status and output current If also the Poll Only P...

Page 12: ...Figure 4 1 Accessing Direct Register Write GUI Overview www ti com 12 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 13: ...Figure 4 2 Direct Register Access View www ti com GUI Overview SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 13 Copyright 2020 Texas Instruments Incorporated ...

Page 14: ...Figure 4 3 Selecting Register Values GUI Overview www ti com 14 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 15: ...by the Main tab such as output voltage control These controls are self explanatory Refer to the LP875761 Q1 data sheet for explanation of the functions See following images for reference of the Config and Advanced tabs www ti com GUI Overview SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 15 Copyright 2020 Texas Instruments Incorporated ...

Page 16: ...ig Tab of the LP8757 GUI Figure 4 6 Advanced Tab of LP8757 GUI GUI Overview www ti com 16 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 17: ...rs can be read or written simply by referring to the logical registers by their name See an example Figure 4 8 The console has a number of integrated macros that are listed in Table 4 3 Figure 4 7 Opening Console www ti com GUI Overview SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 17 Copyright 2020 Texas Instruments Incorporated ...

Page 18: ...me given in ms Useful in loops iout buck number Returns the measured load current of the chosen buck core 0x address data or address bits data I2C read or write command addr value examples 0x12 0xaa 0x12 7 1 0x12 3 0 15 The console supports use of scripts If a text file containing commands supported by the console is stored in the same folder with the evaluation software executable then the script...

Page 19: ...Grade 1 0402 MuRata GCM155R71C104JA55D 23 C10 C11 C12 C13 CAP CERM 390 pF 50 V 5 C0G NP0 AEC Q200 Grade 1 0402 TDK CGA2B2C0G1H391J050BA 4 C14 C18 C22 C26 C37 C45 C53 C61 C95 CAP CERM 0 01 µF 50 V 10 C0G NP0 AEC Q200 Grade 1 0402 MuRata GCM155R71H103KA55D 9 C63 CAP TA 220 µF 10 V 10 0 15 Ω SMD AVX TPSD227K010R0150 1 C64 CAP CERM 100 µF 6 3 V 20 X5R 0805 MuRata GRM21BR60J107M 1 C69 C70 C71 C87 CAP C...

Page 20: ... SH J3 SH J4 SH J5 Shunt 100 mil Gold plated Black TE Connectivity 881545 2 5 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 Test Point Miniature SMT Keystone 5015 14 U1 Four Phase DC DC Buck Converter RNF0026C VQFN HR 26 Texas Instruments LP875761ARNFRQ1 1 U2 AT91SAM ARM based Flash MCU LQFP100 Atmel ATSAM3U2CA AU 1 U3 Dual Linear Regulator with 300 mA and 150 mA Outputs and Power O...

Page 21: ...o the LP875761 Q1 device Figure 6 1 Board Stack Up The design utilizes dual side placement of the components This allows placement of the inductors next to the LP875761 Q1 device for reducing SW node area for improved efficiency and reduced EMI SW nets have also snubber components to reduce SW pin spiking and EMI The input capacitors can be placed very close to the LP875761 Q1 device to bottom sid...

Page 22: ...Figure 6 2 Top View of the LP875761 Q1EVM Board Layout www ti com 22 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 23: ...Figure 6 3 Component Placement Top Layer www ti com Board Layout SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 23 Copyright 2020 Texas Instruments Incorporated ...

Page 24: ...Figure 6 4 Component Placement Bottom Layer Board Layout www ti com 24 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 25: ... and EMI Also snubber circuits are placed next to SW nets for EMI reduction Multiple GND vias are used to provide solid ground around the LP875761 Q1 device Figure 6 5 Top Layer www ti com Board Layout SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 25 Copyright 2020 Texas Instruments Incorporated ...

Page 26: ... inductor footprint SW node to reduce parasitic capacitance of the SW node thus reducing noise coupling and improving efficiency Figure 6 6 Mid Layer1 Board Layout www ti com 26 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 27: ...iated emissions VIN and GND vias are placed in hatched pattern to avoid large gaps in these planes Figure 6 7 Mid Layer2 www ti com Board Layout SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 27 Copyright 2020 Texas Instruments Incorporated ...

Page 28: ...oser placement of the inductors and input components reducing SW and VIN net areas and improving EMI Figure 6 8 Bottom Layer note mirror view Board Layout www ti com 28 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 29: ...VM Schematics Figure 7 1 LP875761Q1EVM Schematic www ti com LP875761Q1EVM Schematics SNVU751 OCTOBER 2020 Submit Document Feedback The LP875761Q1EVM Evaluation Module 29 Copyright 2020 Texas Instruments Incorporated ...

Page 30: ...rs for previous revisions may differ from page numbers in the current version Revision History www ti com 30 The LP875761Q1EVM Evaluation Module SNVU751 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 31: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 32: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 33: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 34: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 35: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 36: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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