3.3 Notes on Efficiency Measurement Procedure
Output Connections: An appropriate electronic load or high-power system source meter instrument, specified for
operation down to 500 mV, is desirable for loading the UUT. The maximum load current is specified as 4 A per
phase. Be sure to choose the correct wire size when attaching the electronic load. A wire resistance that is too
high will cause a voltage drop in the power distribution path which becomes significant compared to the absolute
value of the output voltage. Connect an electric load to J13. It is advised that, prior to connecting the load, it be
set to sink 0 A to avoid power surges or possible shocks.
Voltage drop across the PCB traces will yield inaccurate efficiency measurements. For the most accurate voltage
measurement at the EVM, use J6 (unpopulated through-hole) to measure the input voltage and J1 (unpopulated
through-hole) to measure the output voltage.
To measure the current flowing to/from the UUT, use the current meter of the DC power supply/electric load as
long as it is accurate. Some power source ammeters may show offset of several milliamps and thus will yield
inaccurate efficiency measurements. In order to perform very accurate I
q
measurements on the UUT, disconnect
input protective Zener diode D1 by removing the shunt J5 from the board. When connected, this diode will cause
some leakage, especially on high VIN voltages.
4 GUI Overview
The evaluation software has the following tabs: Main, Config, and Advanced. The three tabs together provide the
user access to the whole register map of the LP875761-Q1. Additional register control can be obtained from
Tools --> Direct Register Access.
4.1 Main Tab
The Main tab (see for example
) has the elemental controls for the EVM and provides a view to the
chip status. Starting from top, the main controls are:
• I2C mode or 4 Enable mode. If this states I2C mode, device is controlled with I2C. When this states 4EN
mode, bucks are controlled with ENx pins.
• Assert NRST: This checkbox will assert high level to LP875761-Q1 NRST pin. This pin enables the chip
internal voltage reference and bias circuitry.
• Assert EN1: This checkbox will assert high level to LP875761-Q1 EN1 pin. Asserting EN1 may enable the
buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN2: This checkbox will assert high level to LP875761-Q1 EN2 pin. Asserting EN2 may enable the
buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN3: This checkbox will assert high level to LP875761-Q1 EN3 pin. Asserting EN3 may enable the
buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN4: In 4 Enable mode, this checkbox will assert high level to LP875761-Q1 SCL pin, (alternative
function is EN4). Asserting EN4 may enable one or more of the buck regulators, depending on the register
settings. This checkbox is visible only when device is configured to 4 Enable Signal Mode.
• Assert SW Reset: To perform a complete SW reset to the chip, assert this checkbox. See the LP875761-Q1
datasheet for explanation of LP875761-Q1 reset scenarios.
Note
The recommended start-up sequence for LP875761Q1 is to first assert NRST, then write all needed
configuration bits by using the GUI, and then enable one or more of th buck regulators by ENx pin or
EN_BUCKx bit.
Quick Setup Guide
10
The LP875761Q1EVM Evaluation Module
SNVU751 – OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
