www.ti.com
Board Layout
5
SNVU542 – July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
LMS36x5x-Q1 EVM User's Guide
3
Board Layout
The LMS3655xQEVM uses a four-layer PCB stack-up design. Top Layer 1 and Bottom Layer 4 are
implemented using 2-oz. copper for optimized heat transfer and dissipation. Mid Layer 2 and Mid Layer 3
use 1-oz. copper. Total PCB thickness is 61 mil (1.55 mm).
Figure 4. Four-Layer PCB Stack-Up
The overall EVM PCB board size dimension is 4000 mil × 3000 mil (101 mm × 76 mm) with a top surface
area of 76 cm
2
. All vias on the PCB are constructed using 8-mil drill through-hole with 16-mil pad size.
Figure 5
to
Figure 8
shows the PCB Layout for each Cu Layer. Top Layer 1 and Bottom Layer 4 are
constructed using large filled Cu areas connected to GND. This is done to improve thermal performance
as well as improve overall EMI performance. Mid Layer 2 is constructed using a large GND plane. The
purpose is to minimize loop inductance by placing metal directly under the Top Layer 1 traces, which
minimizes the cross section of current loops. Mid Layer 3 is mainly used to route non-critical signal traces
to the IC.
NOTE:
The PCB layout is not fully optimized to use for final applications, but gives a good starting
point. The layout can be simplified and optimized by eliminating features included for
evaluation purposes such as measurement sense lines, jumper connections, and features
unused in a particular application such as the feedback resistor divider for fixed voltage
options.
