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Texas Instruments LMK04832EVM-CVAL, User Manual

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Texas Instruments LMK04832EVM-CVAL User Manual Download Page 18

0.1µF

C90

0.1µF

CLKout0

C91

1

5

4

3

2

J29

CLKout0_P

1

5

4

3

2

J30

CLKout0_N

240

R101

0

0

R104

R105

Vcc12_CG0

CLKout0_1_P

240

CLKout0_1_N

R109

120

R120

0

R114

0.1µF

C92

0.1µF

C95

1

5

4

3

2

J31

CLKout2_P

1

5

4

3

2

J34

CLKout2_N

CLKout2

0

R116

0.1µF

C93

0.1µF

C96

1

5

4

3

2

J32

CLKout4_P

1

5

4

3

2

J35

CLKout4_N

CLKout4

0

R118

0.1µF

C94

0.1µF

C97

1

5

4

3

2

J33

CLKout6_P

1

5

4

3

2

J36

CLKout6_N

CLKout6

49.9

R132

49.9

R123

0

R126

0

R127

0.1µF

C98

0.1µF

C101

1

5

4

3

2

J37

CLKout8_P

1

5

4

3

2

J40

CLKout8_N

CLKout8

13nH

R133

13nH

0

R124

R128

20.0

R129

0.1µF

C99

0.1µF

C102

1

5

4

3

2

J38

CLKout10_P

1

5

4

3

2

J41

CLKout10_N

CLKout10

180

R134

180

R125

0

0

R130

R131

0.1µF

C100

0.1µF

C103

1

5

4

3

2

J39

CLKout12_P

1

5

4

3

2

J42

CLKout12_N

CLKout12

EVEN CLOCK OUTPUTS

CLKout0_N

CLKout0_P

CLKout2_P

CLKout2_N

CLKout2_1_N

CLKout2_1_P

Vcc2_CG1

CLKout4_N

CLKout4_P

Vcc4_CG2

CLKout4_1_P

CLKout4_1_N

CLKout6_N

CLKout6_P

Vcc4_CG2

CLKout6_1_P

CLKout6_1_N

CLKout8_N

CLKout8_P

Vcc11_CG3

CLKout8_1_P

CLKout8_1_N

CLKout10_N

CLKout10_P

Vcc11_CG3

CLKout10_1_P

CLKout10_1_N

CLKout12_N

CLKout12_P

Vcc12_CG0

CLKout12_1_P

120

CLKout12_1_N

68nH

R111

68nH

R112

0

R113

R115

20.0

R117

20.0

68nH

R119

68nH

R122

R121

Schematics

www.ti.com

18

SNAU252 – June 2020

Submit Documentation Feedback

Copyright © 2020, Texas Instruments Incorporated

LMK04832EVM-CVAL User’s Guide

Figure 11. Schematic - Clock Outputs 1 of 2

Summary of Contents for LMK04832EVM-CVAL

Page 1: ...ICS Pro to Program the LMK04832 SP 7 6 Evaluation Board Inputs and Outputs 11 7 Recommended Test Equipment 13 8 Length Matching 13 9 Schematics 15 10 Bill of Materials 20 Appendix A TICS Pro Usage 25 List of Figures 1 Quick Start Diagram 3 2 Clock Outputs Page Description Diagram 5 3 Selecting a Default Mode for the LMK04832 SP Device 7 4 Selecting the LMK04832 SP 8 5 Loading the Device 9 6 Settin...

Page 2: ...6 3 Integrated VCO PLL 6 4 Default TICS Pro Modes for the LMK04832 SP 7 5 Description of Evaluation Board Inputs and Outputs 11 6 Differential Pair Lengths 14 7 Bill of Materials 20 Trademarks PLLatinum is a trademark of Texas Instruments All other trademarks are the property of their respective owners 1 Evaluation Board Kit Contents Table 1 lists the components found in the evaluation board kit T...

Page 3: ...out0_P CLKout1_N CLKout1_P CLKout3_N CLKout3_P CLKout2_N CLKout2_P CLKout4_P CLKout4_N GND VCC Default is LDO to IC Program with TICS Pro H VXUH WR SUHVV µ WUO RU USB commination Æ Write All Registers CLKout10_N CLKout10_P CLKout11_N CLKout11_P CLKout13_N CLKout13_P CLKout12_N CLKout12_P Fin0_N Fin0_P CLKout6_P CLKout6_N CLKout7_P CLKout7_N OSCin_P OSCin_N OSCout_P CLKin2_P OSCout_N CLKin2_N CLKin...

Page 4: ... and the EVM 4 Program the device with TICS Pro TICS Pro is available for download at http www ti com tool ticspro sw a Select LMK04832 SP from the Select Device Menu Click Select Device Clock Generator Jitter Cleaner Dual Loop b Select USB2ANY mode from the Communication Setup window To access this select USB communications Interface Confirm that the PC to USB communication is working by clicking...

Page 5: ...DCLKX_Y_DCC Enable duty cycle correct and half step for this device clock divider 10 DCLKX_Y_POL If set polarity of device clock is inverted 11 DCLKX_Y_BYP If set the device clock divider is bypassed for CLKoutX and 15 must be CML 12 CLKoutX_SRC_MUX Select device clock or SYSREF clock path for CLKoutX 13 CLKoutX_Y_IDL Increase input drive level to improve noise floor at cost of power 2 mA 14 SYSRE...

Page 6: ...hase reference The loop filters on the LMK04832EVM CVAL evaluation board are setup using the approach above The loop filter for PLL1 has been configured for a narrow loop bandwidth 1 kHz The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board Table 2 and Table 3 contain the parameters for PLL1 and PLL2 for each oscillator option TI s PLLatinu...

Page 7: ...Y CLKin1 122 88 MHz OSCin 122 88 MHz VCO1 2949 12 MHz Dual PLL Internal VCO 122 88 MHz 122 88 MHz Figure 3 Selecting a Default Mode for the LMK04832 SP Device 5 Using TICS Pro to Program the LMK04832 SP This section will demonstrate how to use TICS Pro For more information on using TICS Pro refer to Appendix A TICS Pro is available for download at http www ti com tool ticspro sw Before proceeding ...

Page 8: ...04832EVM CVAL User s Guide Figure 4 Selecting the LMK04832 SP 5 3 Program the Device To program press Ctrl L Alternatively click USB communications Write All Registers from the menu to program the device to the current state of the register map to the device Ctrl L is the accelerator key assigned to the Write All Registers option and is very convenient ...

Page 9: ...s Ctrl L to restore the default configuration Figure 6 Setting the Default Configuration for LMK04832 SP For the purpose of this walkthrough a default mode will be loaded to ensure a common starting point This is important because when TICS Pro is closed it remembers the last settings used for a particular device Again remember to press Ctrl L as the first step after loading a default mode 5 5 Vis...

Page 10: ...C_MUX 0 Device Clock as desired b While the phase noise of a SYSREF Clock is typically not of concern to configure an output for SYSREF SCLKX_Y_PD 0 in Clock Mode Select box Phase of the SYSREF clock can be adjusted Local digital delay can be set with SCLKX_Y_DDLY Local analog delay can be set by enabling with ADLY_EN 1 SCLKX_Y_ADLY_EN and then setting SCLKX_Y_ADLY to the desired time delay Global...

Page 11: ...lock Outputs CLKout0_P J29 CLKout0_N J30 CLKout1_P J16 CLKout1_N J15 CLKout2_P J31 CLKout2_N J34 CLKout3_P J20 CLKout3_N J17 CLKout4_P J32 CLKout4_N J35 CLKout5_P J21 CLKout5_N J18 CLKout6_P J33 CLKout6_N J36 CLKout7_P J22 CLKout7_N J19 CLKout8_P J37 CLKout8_N J40 CLKout9_P J26 CLKout9_N J23 CLKo ut10_P J38 CLKout10_N J41 CLKout11_P J27 CLKout11_N J24 CLKout12_P J39 CLKout12_N J42 CLKout13_P J28 C...

Page 12: ..._N J10 OSCout_P J11 OSCout_N J12 Fin0_P J3 Fin0_N J4 Analog Input Reference Clock Inputs for PLL1 or PLL1 CLKin0 CLKin1 CLKin2 CLKin1_N is configured by default for a single ended reference clock input from a 50 ohm source The non driven input pin CLKin1_P is connected to GND with a 0 1 uF CLKin0 is configured by default for a differential reference clock input from a 50 ohm source CLKin1 is the d...

Page 13: ... 1 SYNC SYSREF_REQ pin can hold outputs in a low state depending on system configuration SYNC_POL adjusts for active low or active high control A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the SYNC SYSREF page Section A 8 in TICS Pro Status LEDs Status_LD1 TP18 Stat us_LD2 TP21 CMOS Input Output Programmable status output pin By default Status_LD1 and Status_LD2 are set ...

Page 14: ... Length mil Skew CLKout0_P CLKout0_N CLKout1_P CLKout1_N 3977 5 0 5 0 delay Mode Phase Skew CLKin1_P CLKin1_N OSCout_P OSCout_N CLKout6_P CLKout6_N CLKout7_P CLKout7_N CLKout8_P CLKout8_N SYNC 4539 5 0 5 Skew CLKout2_P CLKout2_N CLKout3_P CLKout3_N CLKout4_P CLKout4_N CLKout5_P CLKout5_N CLKout9_P CLKout9_N CLKout10_P CLKout10_N CLKout11_P CLKout11_N CLKout12_P CLKout12_N CLKout13_P CLKout13_N 424...

Page 15: ...cEXT TP2 GND 1 2 J2 VccEXT VccEXT 0 0 R6 R3 0 R5 1 SHDN 2 IN 3 IN 4 IN NC 5 OUT 6 OUT 7 OUT 8 9 GND 10 SENSE ADJ PAD 11 U1 TPS7A4501HKU EM GND 3 6 GND 1 SHDN 2 IN 4 OUT 5 TPS7A4533KTTR SENSE U2 0 R14 GND 0 R15 TP1 Vcc 10µF C25 10µF C24 25V 22uF C12 10µF C14 GND 25V 22uF C13 10µF C15 GND Vcc Vcc Vcc Vcc LDO TP5 GND TP4 GND TP6 GND 120 ohm R18 120 ohm R19 120 ohm R20 120 ohm R21 120 ohm R22 0 0 R8 0...

Page 16: ...4 GND GND Status_LD1 1 S 5tatus_LD2 2 3 4 5 J5 CLKin0_P 1 J14 2 3 4 5 OSCin_N 1 2 3 4 5 J13 OSCin_P 1 2 3 4 5 J4 Fin0_N 1 2 3 4 5 J3 Fin0_P 10V 0 1µF C48 10V 0 1µF C49 49 9 R30 49 9 R32 GND GND 100 R31 1 2 3 4 5 J10 CLKin1_N 1 J8 2 3 4 5 CLKin1_P 10V 0 1µF C51 10V 0 1µF C52 GND GND 100 R35 270 R37 0 R34 CLKin0_P CLKin0_N CLKin1_P CLKin1_N OSCin_P OSCin_N Fin0_P Fin0_N CLKin0_1_P CLKin0_1_N CLKin1_...

Page 17: ...7 1 2 3 4 5 6 7 8 9 10 J43 USB2ANY TP11 CLKin_SEL1 TP10 CLKin_SEL0 TP14 SCK TP17 SDIO TP19 CS TP13 RESET Red 2V 1 2 D1 Red 2V 1 2 D2 1 J44 2 3 4 5 SYNC SYNC to have direct 0 run from SMA to pin without stub R108 TP15 TEST TP20 SYNC 33 R140 IO_LVL_SEL IOLVL TP12 IOLVL Status_LD1 Status_LD2 Status_LD2 270 Status_LD1 R110 270 R102 TP18 Status_LD1 TP21 Status_LD2 Green 2 1V 1 2 D3 Green 2 1V 1 2 D4 TP...

Page 18: ...out10_P 1 5 4 3 2 J41 CLKout10_N CLKout10 180 R134 180 R125 0 0 R130 R131 0 1µF C100 0 1µF C103 1 5 4 3 2 J39 CLKout12_P 1 5 4 3 2 J42 CLKout12_N CLKout12 EVEN CLOCK OUTPUTS CLKout0_N CLKout0_P CLKout2_P CLKout2_N CLKout2_1_N CLKout2_1_P Vcc2_CG1 CLKout4_N CLKout4_P Vcc4_CG2 CLKout4_1_P CLKout4_1_N CLKout6_N CLKout6_P Vcc4_CG2 CLKout6_1_P CLKout6_1_N CLKout8_N CLKout8_P Vcc11_CG3 CLKout8_1_P CLKou...

Page 19: ...LKout7_P CLKout7_1_N CLKout7_1_P CLKout7_N CLKout7_P CLKout7 CLKout9_1_P 240 CLKout9_1_N R97 240 R88 0 R91 0 R92 0 1µF C84 0 1µF C87 1 5 4 3 2 J23 CLKout9_N 1 5 4 3 2 J26 CLKout9_P CLKout9 240 R98 240 R89 0 0 R93 R94 0 1µF C85 0 1µF C88 1 5 4 3 2 J24 CLKout11_N 1 5 4 3 2 J27 CLKout11_P CLKout11_1_N 180 CLKout11 CLKout11_1_P R99 180 R90 0 R95 0 R96 0 1µF C86 0 1µF C89 1 5 4 3 2 J25 CLKout13_N 1 5 4...

Page 20: ...R53 R59 R69 R79 R82 R84 R91 R93 R95 R104 R114 R127 R130 R108 RES 0 5 0 063 W AEC Q200 Grade 0 0402 Vishay Dale CRCW04020000Z0 ED 19 7 C45 C47 CAP CERM 100 pF 25 V 5 C0G NP0 0402 Kemet C0402C101J3GAC TU 2 8 C48 C49 C51 C52 C65 C71 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 CAP CERM 0 1 µF 10 V 10 X7R 0402 Kemet C0402C104K8RAC ...

Page 21: ...11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J41 J42 J44 Connector End launch SMA 50 ohm SMT Cinch Connectivity 142 0701 851 39 25 J43 Header shrouded 100mil 5x2 Gold SMT FCI 52601 S10 8LF 1 26 LBL1 Thermal Transfer Printable Labels 0 650 W x 0 200 H 10 000 per roll Brady THT 14 423 10 1 27 R1 R2 R4 R5 R6 R8 R11 R13 R16 R38 ...

Page 22: ... RES 120 5 0 063 W AEC Q200 Grade 0 0402 Vishay Dale CRCW0402120RJN ED 4 41 R90 R99 R125 R134 RES 180 5 0 063 W AEC Q200 Grade 0 0402 Vishay Dale CRCW0402180RJN ED 4 42 R112 R113 R121 R122 Inductor Multilayer Air Core 68 nH 0 16 A 2 ohm AEC Q200 Grade 1 SMD MuRata LQG15WZ68NJ02D 4 43 R117 R119 R129 RES 20 0 1 0 063 W AEC Q200 Grade 0 0402 Vishay Dale CRCW040220R0FK ED 3 44 R124 R133 Inductor Multi...

Page 23: ...C18 C21 C23 C28 C31 C34 C37 C40 C43 CAP CERM 0 01 uF 25 V 10 X7R 0402 MuRata GCM155R71E103K A37D 0 56 C6 C9 CAP CERM 1 µF 16 V 10 X7R AEC Q200 Grade 1 0603 TDK CGA3E1X7R1C105 K080AC 0 57 C12 C13 CAP TA 22 uF 25 V 10 0 2 ohm SMD Kemet T495D226K025ATE 200 0 58 C29 C32 C35 C38 C41 CAP CERM 10 µF 6 3 V 20 X7R 0603 Samsung Electro Mechanics CL10B106MQ8NRN C 0 59 C50 C53 CAP CERM 270 pF 50 V 10 X7R 0603...

Page 24: ... 68 R50 R70 R80 R81 R83 R92 R94 R96 R105 R115 R116 R118 R126 R128 R131 RES 0 5 0 063 W AEC Q200 Grade 0 0402 Vishay Dale CRCW04020000Z0 ED 0 69 R52 R57 RES 120 5 0 1 W AEC Q200 Grade 0 0603 Vishay Dale CRCW0603120RJN EA 0 70 R88 R89 R97 R98 RES 240 5 0 063 W AEC Q200 Grade 0 0402 Vishay Dale CRCW0402240RJN ED 0 71 R139 R65 R71 R75 RES 27 k 5 0 1 W AEC Q200 Grade 0 0603 Vishay Dale CRCW060327K0JN E...

Page 25: ...the basic purpose and usage of each page TICS Pro is available for download at http www ti com tool ticspro sw A 1 Communication Setup The Communication Setup window allows the USB2ANY or DemoMode to be selected In case multiple evaluation boards are to be connected and run with multiple instances of TICS Pro the drop down box will allow specific USB2ANY devices to be selected Pressing the Identif...

Page 26: ...20 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TICS Pro Usage A 2 User Controls The User Controls page has controls typically not included on one of the other dedicated pages Figure 14 TICS Pro User Controls Page ...

Page 27: ...All registers may be read or written in addition to individual registers For individual register read or write the active register is highlighted in the list of registers and displayed in the top right An individual register or field may be read back by entering the name into the bottom right and clicking the Read button Register maps may be exported but also imported The import format may simply ...

Page 28: ...ode or several registers are already programmed as needed the log will not display any or many register writes The top LMK04832 SP modes section allows the user to set high level usage profiles to allow the device to operate in dual loop single loop or distribution mode The bottom LMK04832 SP sub modes section allows further JESD204B configuration 0 delay configuration or clock input configuration...

Page 29: ...LOS Set LOS_EN 1 checked Set LOS_TIMEOUT combo box to the LOS frequency threshold as desired For example if 200 MHz is set as the frequency threshold the input must be above approximately 200 MHz to lock otherwise PLL1 will enter holdover If holdover is not enabled PLL1 will be prevented from locking if the input frequency is less than the threshold frequency and LOS is enabled In addition to the ...

Page 30: ...ted TICS Pro Usage A 6 CLKinX Control Page The CLKinX Control page allows entry of the input frequency at the different CLKinX pins the mode by which the active CLKinX is selected where the CLKinX inputs are routed to Also on this page are controls to reset the PLL1 R or PLL2 N divider Figure 18 TICS Pro CLKinX Control Page ...

Page 31: ...on to the basic PLL dividers and controls when the PLLX_NCLK_MUX selects the feedback mux as a source 0 delay modes are achieved When enabling 0 delay red text will help guide the user through properly setting up 0 delay mode When using dual PLL mode the OSCin Source combo box can be set to External VCXO which links the OSCin frequency with the external VCXO frequency When using single PLL2 mode t...

Page 32: ... be run after changing the digital delay value which requires a SYNC to update This functionality is also available on any other page through the toolbar as SYNC Dividers NOTE To use SYNC or SYSREF ensure that SYNC_EN 1 To use SYSREF in continuous pulser or reclocked modes be sure SYSREF_PD 0 The SCLKX_Y_DIS_MODE bits allow the clock outputs to be disabled or set to a low state Because values 1 an...

Page 33: ...ol of all the clock outputs format and other options relating to the clock outputs All the clock outputs are paired and allow two device clocks two SYSREF clocks or one of each The naming convention uses X_Y for controls which can impact both CLKoutX even clock and CLKoutY odd clock X for controls impacting only CLKoutX and Y for controls impacting only CLKoutY Figure 21 TICS Pro Clock Outputs Pag...

Page 34: ... A 10 Other Page The Other page contains some registers to control the GPIO pins of the LMK04832 SP Each pin has two fields the first is the _TYPE field which allows the input or output mode of the pin to be defined The second is the _MUX field which when set for output controls what the pin will output Figure 22 TICS Pro Other Page ...

Page 35: ...tputs page but also set the hardware configuration connected to that output With this information along with the other programmed fields a current calculation estimate is made for the LMK04832 SP Also power dissipated externally in emitter resistors and so forth is estimated and subtracted from the total power to find the IC Power the device must dissipate In the lower left is some boxes to accoun...

Page 36: ...une 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TICS Pro Usage A 12 Burst Page The Burst page allows the user to program sequences of register programming or pin control Figure 24 TICS Pro Burst Page ...

Page 37: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 38: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 39: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 40: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 41: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 42: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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