Evaluation Board Inputs and Outputs
12
SNAU252 – June 2020
Copyright © 2020, Texas Instruments Incorporated
LMK04832EVM-CVAL User’s Guide
Table 5. Description of Evaluation Board Inputs and Outputs (continued)
CONNECTOR NAME
SIGNAL TYPE,
INPUT/OUTPUT
DESCRIPTION
OSCout
OSCout_P(J11)
OSCout_N(J12)
Analog,
Output
Buffered outputs of OSCin port.
The output terminations on the evaluation board are shown here.:
OSC Output Pair
Default Board Termination
OSCout
LVPECL, 240
Ω
OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The
OSCout buffer type can be selected in TICS Pro on the
Clock Outputs
page
through the OSCout_FMT control.
Note that OSCout is DC-coupled by default. In case RF test equipment cannot
handle the OSCout voltage, please AC-couple OSCout by replacing C59 and C60
with capacitors.
If OSCout is programmed as LVCMOS, each output can be independently
configured (normal, inverted, inverted, and off/tri-state). Best performance/EMI
reduction is achieved by using a complementary output mode like Norm/Inv. It is
NOT recommended to use Norm/Norm or Inv/Inv mode.
Power
VccEXT(J1/J2/TP3)
Vcc(TP1)
Power,
Input
Main power supply input for the evaluation board.
The LMK04832EVM-CVAL default is setup to use the TPS7A4501HKU/EM voltage
regulator. This is a space grade voltage regulator. 0-ohm resistors R3, R5, R6, R14
and R15 can be re-configured to route power through the on-board commercial
grade LDO, the TPS7A4533KTTR. The LMK04832-SP contains internal voltage
regulators for the VCO and other internal blocks. The clock outputs do not have an
internal regulator, so a clean power supply with sufficient output current capability is
required for optimal performance. If using an external voltage please ensure the
voltage is filtered to get the best performance on the outputs.
Apply power to either Vcc SMA(J1) or terminal block(J2), but not both.
Clock Inputs
CLKin0_P(J5),
CLKin0_N(J6),
CLKin1_P(J8),
CLKin1_N(J10)
OSCout_P(J11),
OSCout_N(J12)
Fin0_P(J3),Fin0_N(J4)
Analog,
Input
Reference Clock Inputs for PLL1 or PLL1 (CLKin0, CLKin1, CLKin2)
CLKin1_N is configured by default for a single-ended reference clock input from a
50-ohm source. The non-driven input pin CLKin1_P is connected to GND with a 0.1
uF. CLKin0 is configured by default for a differential reference clock input from a 50-
ohm source.
CLKin1 is the default reference clock input selected in TICS Pro.
If OSCout is to be used as a CLKin2, then the PCB must be updated to operate as
an input instead of an output.
Clock Distribution with Fin0 or CLKin1/Fin1
Fin0 and CLKin1 (Fin1) are shared for use as an RF Input for Clock Distribution
mode or for an external VCO mode.
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use as an external feedback clock input (FBCLKin) to PLL1 N
or PLL2 N for 0-delay mode. Refer to the
(SNAS698) data sheet for
more details on using 0-delay mode with the evaluation board and the evaluation
board software.
OSCin, PLL2
reference/PLL1
feedback
OSCin_P(J13),
OSCin_N(J14)
Analog,
Input
Feedback VCXO clock input to PLL1 and Reference clock input to PLL2.
The single-ended output of the onboard VCXO (Y1/Y2) drives the OSCin_N input of
the device and the OSCin_P input of the device is connected to GND with 0.1 uF.
VCXO Y1 and Y2 may also be used with differential VCXOs.
An external VCXO may be optionally attached through these SMA connectors with
minor modification to the components going to the OSCin pins of device.
A single-ended or differential signal may be used to drive the OSCin pins and must
be AC coupled. If operated in single-ended mode, the unused input must be
connected to GND with 0.1 uF.
Refer to the
(SNAS698) data sheet section “Electrical
Characteristics” for PLL2 Reference Input (OSCin) specifications (SNAS698).
VCO Tuning Voltages
VTUNE1 (TP7/J7)
VTUNE (TP8/J9)
Analog,
Input/Output
Tuning voltage output from the loop filter for PLL1 and PLL2 of the LMK04832-SP.
If an external VCXO is used, this tuning voltage can be connected to the voltage
control pin of the external VCXO.
The default board does not come with J7 and J9 populated.