Texas Instruments LMK03328EVM User Manual Download Page 36 | Manualshive

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1

2

3

4

5

J11

OUT1_P

1

2

3

4

5

J12

OUT1_N

1

2

3

4

5

J10

OUT0_N

OUT0_P

1

2

3

4

5

J9

OUT0_P

0

R56

DNP

0

R57

DNP

0

R58

DNP

1

2

3

4

5

J13

OUT2_P

1

2

3

4

5

J14

OUT2_N

0

R60

DNP

OUT0_N

OUT1_P

OUT1_N

OUT2_P

OUT2_N

1

2

3

4

5

J15

OUT3_P

1

2

3

4

5

J16

OUT3_N

0

R62

DNP

OUT3_P

OUT3_N

1

2

3

4

5

J19

OUT5_P

1

2

3

4

5

J20

OUT5_N

1

2

3

4

5

J18

OUT4_N

OUT4_P

1

2

3

4

5

J17

OUT4_P

1

2

3

4

5

J21

OUT6_P

1

2

3

4

5

J22

OUT6_N

OUT4_N

OUT5_P

OUT5_N

OUT6_P

OUT6_N

1

2

3

4

5

J23

OUT7_P

1

2

3

4

5

J24

OUT7_N

OUT7_P

OUT7_N

CLOCK OUTPUTS

0

R76

DNP

0

R78

DNP

0

R80

DNP

0

R82

DNP

0.1µF
0402

C68

0.1µF
0402

C69

0.1µF
0402

C70

0.1µF
0402

C71

0.1µF
0402

C72

0.1µF
0402

C73

0.1µF
0402

C74

0.1µF
0402

C75

0.1µF
0402

C76

0.1µF
0402

C77

0.1µF
0402

C78

0.1µF
0402

C79

0.1µF
0402

C80

0.1µF
0402

C81

0.1µF
0402

C82

0.1µF
0402

C83

50-ohm (+/-5%) single-ended RF traces

0402

0

R44

0
0402

R64

0402

0

R45

0
0402

R46

0
0402

R47

0
0402

R48

0
0402

R49

0
0402

R50

0
0402

R51

0
0402

R65

0
0402

R66

0
0402

R67

0
0402

R68

0
0402

R69

0
0402

R70

0
0402

R71

R_OUT0_P

R_OUT0_N

R_OUT1_P

R_OUT1_N

R_OUT2_P

R_OUT2_N

R_OUT3_P

R_OUT3_N

R_OUT4_P

R_OUT4_N

R_OUT5_P

R_OUT5_N

R_OUT6_P

R_OUT6_N

R_OUT7_P

R_OUT7_N

CLOCK OUTPUT (OUT#_P, OU T#_N) LAYOUT REQUIREMENTS:
*** CONTROLLED IMPEDANCE ***
- Route as 50-ohm (+/-5% tol.) controlled-impedance single-ended RF traces from DUT pin to SMA center pin.
- Place component pads directly on RF traces (no stubs), match 50-ohm trace width to SMA center pad (25 mils wide), and use 50-ohm Zo via structures.
*** LENGTH / SKEW MATCHING ***
- Match output path lengths between all OUT#_P/_N pairs from DUT to SMA pins (Minimize inter-pair or intra-pair skew).
*** SHIELDING / ISOLATION ***
- Use ground shielding on routing layers with sufficient clearance to not affect controlled impedance of RF traces.
- Use ground stitching vias with 100 mil spacing around RF traces to connect GND shielding on all layers.
- Use sufficient clearance between OUT# paths, as well as from other dynamic signal paths.
- Avoid crossing Digital signal/return paths with clock OUT signal/return paths; if unavoidable, cross at a 90 deg. angle

1

2

3

4

5

J25

STAT0

1

2

3

4

5

J26

STAT1

STATU S OUTPUT (STAT0, STAT1) LAYOUT REQUIREMENTS:
*** CONTROLLED IMPEDANCE ***
- Route as 50-ohm (+/-5% tol.) controlled-impedance single-ended RF traces from DUT pin to SMA center pin.
- Place component pads directly on RF traces (no stubs), match 50-ohm trace width to SMA center pad (25 mils wide), and use 50-ohm Zo via structures.
*** LENGTH / SKEW MATCHING ***
- Match status output path lengths between STAT0 and STAT1 paths from DUT to SMA pins.
*** SHIELDING / ISOLATION ***
- Use ground shielding on routing layers with sufficient clearance to not affect controlled impedance of RF traces.
- Use ground stitching vias with 100 mil spacing around RF traces to tie together GND shielding on all layers.
- Use sufficient clearance between STAT0 and STAT1 paths, as well as from other RF paths.
- Avoid crossing Digital signal/return paths with STATU S signal/return paths; if unavoidable, cross at a 90 deg. angle

R_STAT0

STAT0

STAT1

R_STAT1

STATUS OUTPUTS

0.1µF
0402

C86

0.1µF
0402

C87

8.2pF

0402

C84

DNP

8.2pF

0402

C85

DNP

I=2mA

Yell ow

1

2

D6

STAT0=LO

510

R86

I=2mA

Yell ow

1

2

D7

STAT1=LO

510

R87

STAT0_SW

STAT1_SW

0
0402

R84

0
0402

R85

0
0402

R88

0
0402

R90

VDD_R

4.99k

R89

DNP

4.99k

R91

DNP

1

4

S3A

2

3

S3B

SMA_OUT0_P

SMA_OUT0_N

SMA_OUT1_P

SMA_OUT1_N

SMA_OUT2_P

SMA_OUT2_N

SMA_OUT3_P

SMA_OUT3_N

SMA_OUT4_P

SMA_OUT4_N

SMA_OUT5_P

SMA_OUT5_N

SMA_OUT6_P

SMA_OUT6_N

SMA_OUT7_P

SMA_OUT7_N

SMA_STAT0

SMA_STAT1

100

R52

100

R53

100

R54

100

R55

100

R72

100

R73

100

R74

100

R75

0

R59

DNP

0

R61

DNP

0

R63

DNP

0

R77

DNP

0

R79

DNP

0

R81

DNP

0

R83

DNP

EVM Schematic

36

LMK03328EVM User’s Guide

SNAU184 – August 2015

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Copyright © 2015, Texas Instruments Incorporated

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Summary of Contents for LMK03328EVM

Page 1: ...LMK03328EVM User s Guide Literature Number SNAU184 August 2015 ...

Page 2: ...ing the Status Outputs 17 4 7 Using the USB Interface Connection 17 5 EVM Quick Start Guide 18 6 EVM Layout 20 7 EVM Schematic 33 8 EVM Bill of Materials 39 9 Recommended Test Instruments 42 10 Example Performance Measurements 43 11 Using TI s USB2ANY Module for In System Programming of LMK03328 47 11 1 USB2ANY Board Connections 47 11 2 Ordering a USB2ANY Module 51 2 Table of Contents SNAU184 Augu...

Page 3: ... Top 29 16 Bottom Solder Mask 30 17 Bottom Overlay 31 18 Drill Drawing 32 19 Soft Pin Mode EEPROM Page 5 OUT0 156 25 MHz LVPECL Spurs On 43 20 Soft Pin Mode EEPROM Page 5 OUT3 125 MHz LVPECL Spurs On 44 21 Soft Pin Mode EEPROM Page 5 OUT5 133 33 MHz LVPECL Spurs On 45 22 Soft Pin Mode EEPROM Page 5 OUT7 125 MHz LVPECL Spurs On 46 23 USB2ANY Module 47 24 USB2ANY Board Connections 48 25 10 pin Cable...

Page 4: ...nterfaces for Hard Pin Mode JP18 HWCTRL HI 15 5 PLL Loop Filter C2 Selection 15 6 Soft Pin Mode EEPROM Page Configurations EVM Default EEPROM Image 19 7 Output RMS Jitter Summary Soft Pin Mode EEPROM Page 5 43 8 USB2ANY Board Connector J4 and 10 pin Cable Pinouts 50 4 List of Tables SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 5: ...r s Guide SNAU184 August 2015 LMK03328EVM User s Guide Figure 1 LMK03328EVM Photo 5 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 6: ...port import Register and EEPROM data files to facilitate factory or in system programming of custom device configurations 2 Features Two independent clock domains in Dual PLL operation for clocking multiple interface standards protocols Outputs up to 8 pairs of Differential or 1 8V LVCMOS clocks or any combination of both 100 Ω differential and 50 Ω single ended output drivers PLLs can lock to a c...

Page 7: ...ister Default Mode Loads all registers from the register default setting The Register Default Mode is hard coded with predefined settings NOTE Refer to the Register Default Mode in the LMK03328 datasheet The Register Default Mode will NOT operate using the on board 50 MHz crystal Y1 as the device expects a 25 MHz reference input To operate in Register Default Mode using a crystal input Y1 must be ...

Page 8: ...Configuring the EVM www ti com Figure 2 Power Input and Output Connections 8 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 9: ...s U3 U4 can allow a higher supply voltage like 5 V to power the EVM and jumper selection of the VDDO voltage The direct external supplies or on board regulator supplies can be independently routed for the VDD and VDDO planes by configuring the power terminals and jumpers shown in Figure 3 J3 PWR is the main power terminal block for the EVM for connecting power and GND leads from an external power ...

Page 10: ... to N A N A operate regulators Tie pins 2 3 Tie pins 2 3 Tie pins 1 2 JP2 VDD Selects 3 3 V directly from Selects 3 3 V directly from Selects VDD 3 3 V from U3 EXTVDD EXTVDD Tie pins 1 2 Tie pins 2 3 Tie pins 2 4 JP3 J4 2 VDDO Selects VDDO 1 8 2 5 3 3 Selects 1 8 2 5 3 3 V Selects 3 3 V from VDD V from U4 directly from EXTVDDO Open JP8 Default Selects VDDO 1 8 V Tie pins 1 2 JP8 LDOSEL U4 N A N A ...

Page 11: ...low state by strapping the center pin to HI position tie pins 1 2 or LO position tie pins 2 3 respectively Jumpers JP17 JP20 JP21 and JP22 can be used to configure the control pin with 3 level input scheme where VLO 0 4V VMID 0 9V VHI 1 4V Each of these 4 jumpers use a resistor divider network to bias the control pin to a mid level state of 0 9 V when the jumper is left open MID position The LMK03...

Page 12: ...t 2 JP Default 1 RSEL is ignored when INSEL_PLLx bits 01b 2 In Auto Select mode PRIREF is prioritized over SECREF when a valid signal is detected by the on chip reference detector logic To use the SECREF input in Auto Select mode the input signal to PRIREF must be made invalid disabled or disconnected SYNC pin active low GPIO0 can be used to mute the output clocks when asserted and trigger output ...

Page 13: ...g when permitted by the MARGIN_OPTION register setting R86 3 2 as follows XO MARGIN PIN CONTROL GPIO4 STATE MARGIN_OPTION 00b MARGIN_OPTION 01b Default GPIO4 JP23 XO Margining is enabled 2 level input LO GPIO5 pin selects XO Margining XO Margining is enabled offset 1 GPIO5 pin selects XO Margining offset 1 HI XO Margining disabled JP Default GPIO5 pin is ignored 2 1 See the description for JP24 GP...

Page 14: ...F 2 Applies only to Soft Pin Mode using the EVM s default EEPROM settings optimized for a 9 pF crystal For Register Default Mode refer to the datasheet for the default XOOFFSET_STEP register settings PDN push button switch When pressed the device PDN pin active low is pulled down to power down the device When released the PDN pin is pulled high to trigger the POR sequence initialize the registers ...

Page 15: ...odification areas may include the crystal Y1 PRIREF SECREF input interfaces OUT STATUS output interfaces and PLL1 PLL2 loop filter C2 capacitor selection switches S1 S2 3 GPIO 5 0 values are BCD representation of the ROM Page value 4 3 Configuring the PLL Loop Filters Each PLL of the LMK03328 has configurable PLL loop bandwidth with most loop filter components integrated on chip C1 R2 C3 and R3 On...

Page 16: ...a different crystal is required for the intended configuration e g Register Default or Hard Pin mode configurations remove the original crystal on Y1 and install the new part The new part should comply with the recommended crystal characteristics specified in the LMK03328 datasheet If using a crystal with high load capacitance spec e g 18 pF external trim capacitors may be installed on C58 and C59...

Page 17: ... V even with VDDO of 2 5 V or 3 3 V since the LDOs step down the output driver supply to 1 8 V internally 4 6 Configuring the Status Outputs The STATUS0 and STATUS1 outputs of LMK03328 are configured as 3 3 V LVCMOS by default and are routed via 50 ohm single ended traces to SMA ports STAT0 and STAT1 through AC coupling capacitors The status pins can also be connected to yellow LEDs D6 and D7 thro...

Page 18: ... any input clock to PRIREF SMAs 5 Toggle the PDN push button switch to restart the device in the selected mode 6 Observe any active output clock on OUT 7 0 SMA ports or STAT 1 0 SMA ports a All clock and status outputs are AC coupled to the SMAs b Use 50 ohm coax cables to connect the test equipment to the output SMA ports If making a single ended measurement on a differential output terminate the...

Page 19: ...Value 3300 pF 0 033 uF N A N A N A 3300 pF 312 5 MHz 155 52 MHz 156 25 MHz 125 MHz 156 25 MHz 156 25 MHz OUT0 LVPECL LVPECL CML LVPECL LVPECL LVPECL 312 5 MHz 155 52 MHz 156 25 MHz 125 MHz 156 25 MHz 156 25 MHz OUT1 LVPECL LVPECL CML LVPECL LVPECL LVPECL 156 25 MHz 125 MHz 156 25 MHz 156 25 MHz 156 25 MHz 125 MHz OUT2 LVPECL LVPECL CML LVPECL LVPECL LVPECL 156 25 MHz 125 MHz 156 25 MHz 156 25 MHz ...

Page 20: ...EVM Layout www ti com 6 EVM Layout Figure 6 Top Overlay 20 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 21: ...www ti com EVM Layout Figure 7 Top Solder Mask 21 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 22: ...EVM Layout www ti com Figure 8 Layer 1 Top Side 22 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 23: ...www ti com EVM Layout Figure 9 Layer 2 23 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 24: ...EVM Layout www ti com Figure 10 Layer 3 24 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 25: ...www ti com EVM Layout Figure 11 Layer 4 25 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 26: ...EVM Layout www ti com Figure 12 Layer 5 26 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 27: ...www ti com EVM Layout Figure 13 Layer 6 27 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 28: ...EVM Layout www ti com Figure 14 Layer 7 28 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 29: ...www ti com EVM Layout Figure 15 Layer 8 Bottom Side View from Top 29 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 30: ...EVM Layout www ti com Figure 16 Bottom Solder Mask 30 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 31: ...www ti com EVM Layout Figure 17 Bottom Overlay 31 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 32: ...EVM Layout www ti com Figure 18 Drill Drawing 32 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 33: ... Digital and Power routing Ground flood FR4 16 mil Layer 5 Split Power plane FR4 5 mil Layer 6 Ground Plane FR406 7 mil Layer 7 Ground Plane FR406 7 mil Layer 8 RF microstrip traces from SMAs to DUT Digital and Power routing Ground flood CONTROLLED IMPEDANCE TRACES EXTERNAL 11 mil traces to be 50 ohm Zo 10 INTERNAL 6 mil traces to be 50 ohm Zo 10 TOP 25 mil traces to be 50 ohm Zo 10 ref to Layer 3...

Page 34: ...sed to provide low power supply impedance over a wide frequency range for general evaluation A ferrite bead and bulk cap may be shared to supply multiple output banks with the same PLL frequency but each VDDO pin should have its own bypass cap 3 way Header Alignment 1 pin header is adjacent to center pin of 3 pin header and is the 4th pin 33k R7 33k R8 10µF C21 VDDPLL1 0 1µF 0402 C28 0 1µF 0402 C2...

Page 35: ...top side LF1 0 R42 3 4 S2C LF2 2 5 S2B LF2 1 6 S2A LF2 LF2 0 R43 0 033µF C64 0 033µF C65 CLOCK INPUT PRIREF_P _N SECREF_P _N LAYOUT REQUIREMENTS CONTROLLED IMPEDANCE Route as 50 ohm 5 tol controlled impedance single ended RF traces from SMA center pin to DUT pin Place component pads directly on RF traces no stubs match 50 ohm trace width to SMA center pad and use 50 ohm Zo via structures LENGTH SK...

Page 36: ...th 100 mil spacing around RF traces to connect GND shielding on all layers Use sufficient clearance between OUT paths as well as from other dynamic signal paths Avoid crossing Digital signal return paths with clock OUT signal return paths if unavoidable cross at a 90 deg angle 1 2 3 4 5 J25 STAT0 1 2 3 4 5 J26 STAT1 STATU S OUTPUT STAT0 STAT1 LAYOUT REQUIREMENTS CONTROLLED IMPEDANCE Route as 50 oh...

Page 37: ... 4V HI VIN 1 4V GPIO5 can be an 8 level input pin in XO MARGIN mode GPIO5 Jumper should be left OPEN 0V 0 ohm pulldown only 0 2V 2 32k pulldown only 0 4V 5 62k pulldown only 0 6V 10 5k pulldown only 0 8V 18 7k pulldown only 1 0V 34 8k pulldown only 1 2V 84 5k pulldown only 1 4V OPEN 1 00k R92 1 2 3 JP17 RSEL VDD_R 1 00k R95 1 2 3 JP18 HWCTRL VDD_R 13 0k R93 VDD_R 4 99k R97 DNP 13 0k R96 DNP VDD_R ...

Page 38: ... 68 P5 2 XT2IN 69 P5 3 XT2OUT 70 TEST SBWTCK 71 PJ 0 TDO 72 PJ 1 TDI TCLK 73 PJ 2 TMS 74 PJ 3 TCK 75 RST NMI SBWTDIO 76 P6 0 CB0 A0 77 P6 1 CB1 A1 78 P6 2 CB2 A2 79 P6 3 CB3 A3 80 U8 MSP430F5529IPN 0 1µF C102 0 1µF C101 0 1µF C98 PUR 3 3V 0 47µF C99 VBUS VUSB U2A_GPIO7 Features not supported by On board USB2ANY hardware Switched 3 3V_EXT supply TPS7A8001 LDOs can be switched via USB5V supply GPIO2...

Page 39: ...20 X7R TDK C3216X7R1A106M 5 1206 C49 C50 R29 R30 R31 RES 0 5 0 063 W 0402 Vishay Dale CRCW04020000Z0ED 10 R32 R40 R41 R44 R45 C62 C63 CAP CERM 22 µF 6 3 V 20 X5R TDK C1608X5R0J226M080AC 2 0603 C64 C65 CAP CERM 0 033 µF 16 V 10 MuRata GRM188R71C333KA01D 2 X7R 0603 C66 C67 CAP CERM 3300 pF 50 V 5 MuRata GRM1885C1H332JA01D 2 C0G NP0 0603 C9 C10 C11 C12 C88 CAP CERM 1uF 10V 10 X5R Kemet C0603C105K8PAC...

Page 40: ...ay Dale CRCW060334K8FKEA 1 R123 RES 84 5 k 1 0 1 W 0603 Vishay Dale CRCW060384K5FKEA 1 R13 R15 RES 4 99 k 1 0 1 W 0603 Vishay Dale CRCW06034K99FKEA 2 R14 RES 1 62 k 1 0 1 W 0603 Vishay Dale CRCW06031K62FKEA 1 R141 R142 RES 33 ohm 5 0 063W 0402 Vishay Dale CRCW040233R0JNED 2 R143 RES 1 5k ohm 5 0 063W 0402 Vishay Dale CRCW04021K50JNED 1 R144 RES 1 2Meg ohm 5 0 1W 0603 Vishay Dale CRCW06031M20JNEA 1...

Page 41: ... DCK0006A U10 PRECISION ADJUSTABLE CURRENT Texas Instruments TPS2553DBV 1 1 LIMITED POWER DISTRIBUTION SWITCHES DBV0006A U3 U4 Low Noise Wide Bandwidth High PSRR Texas Instruments TPS7A8001DRB 2 Low Dropout 1A Linear Regulator DRB0008A U5 Ultra Low Jitter Clock Generator Family Texas Instruments LMK03328RHSR 1 with Two Independent PLLs Up to 8 Differential Outputs Two Inputs RHS0048A U6 4 CHANNEL ...

Page 42: ...034K99FKEA 0 R96 R115 RES 13 0k ohm 1 0 1W 0603 Vishay Dale CRCW060313K0FKEA 0 SH4 SH5 SH6 SH7 SH8 Shunt 100mil Gold plated Black 3M 969102 0000 DA 0 SH9 SH10 SH11 SH12 SH13 SH14 TP1 TP2 TP3 TP8 TP9 Test Point Miniature Red TH Keystone 5000 0 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP23 TP20 TP21 TP22 Test Point Miniature Orange TH Keystone 5003 0 TP4 TP5 TP6 TP7 Test Point Compact Black...

Page 43: ...ary Soft Pin Mode EEPROM Page 5 RMS Jitter fs 12k 20M RMS Jitter fs 12k 20M Output Output Frequency Type Reference Plot band spurs off band spurs on OUT0 156 25 MHz LVPECL 103 116 Figure 19 OUT1 156 25 MHz LVPECL 104 128 OUT2 125 MHz LVPECL 104 130 OUT3 125 MHz LVPECL 102 114 Figure 20 OUT4 133 33 MHz LVPECL 98 132 OUT5 133 33 MHz LVPECL 98 120 Figure 21 OUT6 100 MHz LVPECL 136 143 OUT7 100 MHz LV...

Page 44: ...nce Measurements www ti com Figure 20 Soft Pin Mode EEPROM Page 5 OUT3 125 MHz LVPECL Spurs On 44 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 45: ... Performance Measurements Figure 21 Soft Pin Mode EEPROM Page 5 OUT5 133 33 MHz LVPECL Spurs On 45 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 46: ...nce Measurements www ti com Figure 22 Soft Pin Mode EEPROM Page 5 OUT7 125 MHz LVPECL Spurs On 46 LMK03328EVM User s Guide SNAU184 August 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 47: ...rmware as the one integrated on the LMK03328EVM the same EVM GUI platform can be used to easily program the device in system Once the customer s system software firmware is enabled and can provide reliable configuration of the LMK03328 then the provisional I2C header may be removed or superseded in the next iteration of the hardware design 11 1 USB2ANY Board Connections The USB2ANY has four interf...

Page 48: ...otch above J4 that will prevent the cable connector from being plugged in upside down With the notch at the top pin 1 of the 10 pin cable connector is located at the upper right corner The 10 pin cable is about 6 inches in length and has a keyed female 10 pin IDC connector on each end The cable should be connected to the USB2ANY board as shown in Figure 25 note that the key must be facing up away ...

Page 49: ...ule for In System Programming of LMK03328 Figure 25 10 pin Cable Connection to J4 Figure 26 10 pin Cable Pinout 49 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 50: ... output power supply 100 mA limit P4 4 GPIO4 SPI SIM0 7 4 General purpose digital I O not required P4 5 GPIO5 SPI SM01 8 3 General purpose digital I O not required P2 0 GPIO6 SPI CS 9 2 General purpose digital I O not required P1 2 GPIO7 10 1 General purpose digital I O not required Instead of using the 10 pin header and supplied cable a board designer may alternatively choose to use a 3 pin I2C h...

Page 51: ...ck_support list ti com with the following information 1 Request Reason 1 pc USB2ANY module for LMK03328 in system programming prototyping 2 Company Name 3 Application End Equipment 4 LMK03328 Est Annual Volume Year 5 Ship To Address 51 SNAU184 August 2015 LMK03328EVM User s Guide Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 52: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Page 53: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Page 54: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Page 55: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Page 56: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

Page 57: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments LMK03328EVM ...

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