Configuring the EVM
Table 3. Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL =
LO) (continued)
NAME
COMPONENT
DESCRIPTION
(TYPE)
Page Select pins for Soft Pin Mode or Register Default Mode
With HWCTRL = LO, GPIO[3:2] pins are sampled on POR and select the EEPROM page or Register
Default settings to initialize the registers as follows:
GPIO3 STATE
GPIO2 STATE
DEVICE MODE / PAGE SELECT
(1) (2)
LO
LO
Soft Pin Mode, EEPROM Page 0
LO
MID
Soft Pin Mode, EEPROM Page 1
LO
HI
Soft Pin Mode, EEPROM Page 2
GPIO2
HI
LO
Soft Pin Mode, EEPROM Page 3
JP21
GPIO3
JP22
HI
MID
Soft Pin Mode, EEPROM Page 4
(3-level inputs)
HI
HI
Soft Pin Mode, EEPROM Page 5
(JP Default)
(JP Default)
MID
MID
Register Default Mode
(1)
Refer to
for Soft Pin Mode configurations pre-programmed to the EEPROM for EVM
demonstration purposes.
(2)
Register Default Mode will not operate using the on-board 50 MHz crystal (Y1) as the device expects
a 25 MHz reference input. To use Register Default Mode with a crystal input, Y1 must be changed to a
25-MHz 9-pF crystal (example P/N: TXC 7M25072001).
XTAL Frequency Margining Enable pin
GPIO4 can be used to enabled the XTAL frequency margining when permitted by the
MARGIN_OPTION register setting (R86[3:2]) as follows:
XO MARGIN PIN CONTROL
GPIO4 STATE
MARGIN_OPTION=00b
MARGIN_OPTION=01b
(Default)
GPIO4
JP23
XO Margining is enabled.
(2-level input)
LO
GPIO5 pin selects XO Margining
XO Margining is enabled.
offset.
(1)
GPIO5 pin selects XO Margining
offset.
(1)
HI
XO Margining disabled.
(JP Default)
GPIO5 pin is ignored.
(2)
(1)
See the description for JP24 (GPIO5) and switch S5 (XO MARGIN).
(2)
XOOFFSET_STEP4 register setting sets the XTAL load capacitance
XTAL Frequency Margining Offset Select pin
GPIO5 can be used to select the one of the 8 on-chip XTAL load capacitance settings on the crystal
input (SECREF input) when XTAL frequency margining is enabled by the MARGIN_OPTION register
GPIO5
and JP23 setting (GPIO4). The 8 load capacitance settings are programmable (by XOOFFSET_STEP#
JP24
(8-level input)
register settings) and initialized from the selected operating mode/page setting. The 8-level input state
can be configured by selecting one of the pull-down resistors through switch S5.
By default, JP24 is left open, so switch S5 can be used to set the frequency margining offset. See the
description for S5 (XO MARGIN).
SYNC push-button switch
S4
SYNC
When pressed, the GPIO0 pin is pulled down to assert SYNC.
13
SNAU184 – August 2015
LMK03328EVM User’s Guide
Copyright © 2015, Texas Instruments Incorporated
