R
L
OFF2
<
I
V
LED
O
x
0.1 x
C7 x
LED+
PWM2
5V
R4
C9
R3
R2
R1
Q3
Q2
C5
GND2
LED-
EN
LM3409/09HV
I
LED
P
=
F
0
.
1
C4
Shunt FET Circuit Modification
www.ti.com
(37)
Figure 4. External shunt FET dimming circuit with EN pin coupling
7
Shunt FET Circuit Modification
When the shunt FET (Q3) is on, the LM3409 is driving current into a short, therefore a maximum off-time
(typical 300 µs) occurs followed by a minimum on-time. Maximum off-time followed by minimum on-time
continues until Q3 is turned off. At low dimming frequencies and depending on the duty cycle, the inductor
current may be at a very low level when the Q3 turns off. This will eliminate the benefits of using the shunt
FET over the EN pin because the inductor will have to slew the current back to the nominal value
anyways.
A simple modification to the external parallel FET dimming circuit will keep the inductor current close to its
nominal value when Q3 is turned off. This modification will ensure that the rise time of the LED current is
only limited by the turn-off time of the shunt FET as desired. The following circuit additions allow for two
different off-times to occur. When Q3 is off, the standard off-timer referenced from V
O
is set. However
when the Q3 is on, a second off-timer referenced to the gate signal of the Q3 is enabled and a controlled
(non-maximum) off-time is set.
This modification includes 2 extra diodes (i.e. BAT54H) and one resistor (R
OFF2
) and is only relevant when
shunt FET PWM dimming below 10 kHz or so. In general, this second off-timer should be set to allow the
inductor current to fall no more than 10% of its nominal value. A simple approximation can be used to find
R
OFF2
:
(38)
10
AN-1953 LM3409HV Evaluation Board
SNVA390D – May 2009 – Revised May 2013
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