NMOS
8,
SOIC
100V,7.5A,
Q3
CMOS
6,
SOT
30V, 20A,
Q2
100
:
R4
R3
1
:
R2
R1
2.2 nF
C9
F
0.1
C6
-
o
-
o
=
=
=
=
=
=
#
10 k
:
=
=
t
R4
C
=
:
100
nF
2.2
ns
220
C9
1
2
3
1
2
1: No PWM, EN = V
IN
2: External PWM, EN coupled
3: Internal PWM, using EN
3
J1
:
=
P
=
k
1
R10
F
1
.
0
C6
www.ti.com
Design Procedure
The chosen components from step 9 are:
(34)
6.11 PWM Dimming Method
The LM3409HV evaluation board allows for PWM dimming to be evaluated as follows:
Method #1: If no PWM dimming is desired, a jumper should be placed in position 1 (shorts pins 1 and 2)
on header J1. This shorts VIN and EN which ensures the controller is always enabled if an input voltage
greater than 1.74V is applied.
Method #2: External parallel FET shunt dimming can be evaluated by placing the jumper in position 2
(shorts pins 2 and 3) on header J1. This connects the capacitive coupling circuit to the EN pin as
suggested in the datasheet. The resistor (R4) can be solved for assuming a standard capacitor value C9 =
2.2nF and a desired time constant (t
C
= 220ns < t
OFF
) as follows:
(35)
The external shunt FET dimming circuit shown below is designed using an N-channel MosFET (Q3), a
CMOS FET (Q2), two gate current limiting resistors (R1 and R2), a pull-up resistor (R3), and a bypass
capacitor (C5). With an external 5V power supply attached to the 5V terminal and an external PWM signal
attached to the PWM2 terminal, the shunt dimming circuit is complete. Q3 is the shunt dimFET which
conducts the LED current when turned on and blocks the LED voltage when turned off. Q3 needs to be
fast and rated for V
O
and I
LED
. For design flexibility, a fast 100V, 7.5A NFET is chosen. Q2 is necessary to
invert the PWM signal so it properly translates the duty cycle to the shunt dimming FET. Q2 also needs to
be fast and rated for 5V and fairly small current, therefore a 30V, 2A fast CMOS FET was chosen. R1 and
R2 are 1
Ω
resistors to slow down the rising edge of the FETs slightly to prevent the gate from ringing. R3
is a 10k
Ω
pull-up resistor to ensure the CMOS gate is pulled all the way to 5V if a sub-5V PWM signal is
applied to PWM2. The bypass capacitor (C5) for the 5V power supply is chosen to be 0.1µF. See
Section 7
for an improvement that can be made to this circuit.
Method #3: Internal PWM dimming using the EN pin can be evaluated by removing the jumper from
header J1. An external PWM signal can then be applied to the EN terminal to provide PWM dimming.
Section 8
shows typical LED current waveforms during both types of PWM dimming.
The chosen components from step 10 are:
(36)
6.12 Bypass Capacitor
The internal regulator requires at least 1µF of ceramic capacitance with a voltage rating of 16V.
The chosen component from step 11 is:
9
SNVA390D – May 2009 – Revised May 2013
AN-1953 LM3409HV Evaluation Board
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
