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A1
A2
A3
D1
D2
B1
B2
B3
C1
C2
C3
D3
A1
A2
A3
D1
D2
D3
B1
B2
B3
C1
C2
C3
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Connection Diagram and Package Mark Information
9
Connection Diagram and Package Mark Information
Figure 7. Connection Diagram and Package Marking 12-Bump Thin DSBGA Package
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Pin Descriptions
Pin #
Name
Description
A1
NC
Non connection. Leave this pin floating; do not connect to PVIN or PGND.
B1
VCON
Voltage Control Analog input. VCON controls the output voltage in PWM and PFM modes.
Feedback input to inverting input of error amplifier. Connect output voltage directly to this node
C1
FB
at load point.
Regulated output voltage of LM3269. Connect this to a 4.7
μ
F ceramic output filter capacitor to
D1
VOUT
GND.
A2
NC
Non connection. Leave this pin floating; do not connect to PVIN or PGND.
B2
EN
Enable Pin. Pulling this pin higher than 1.2V enables part to function.
C2
SGND
Signal Ground for analog circuits and control circuitry.
D2
SW2
Switch pin for Internal Power Switches. Connect inductor between SW1 and SW2
Power MOSFET input and power current input pin. Optional low-pass filtering may help buck
A3
PVIN
and buck-boost modes for radiated EMI and noise reduction.
Power MOSFET input and power current input pin. Optional low-pass filtering may help buck
B3
PVIN
and buck-boost modes for radiated EMI and noise reduction.
C3
SW1
Switch pin for Internal Power Switches. Connect inductor between SW1 and SW2.
D3
PGND
Power Ground for Power MOSFETs and gate drive circuitry.
5
SNVU162 – FEBRUARY 2013
LM3269 Evaluation Board
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