TP12
TP22
TP32
VS2
VS2
VS2
GND2
GND2
GND2
VS2
GND2
10.0k
R12
0.1
µ
F
C22
0.1
µ
F
C92
0.1
µ
F
C32
GND2
0
R52
0
R62
0.1
µ
F
C42
0
R72
GND2
10.0k
R22
0.1
µ
F
C52
GND2
NC
1
NC
2
IN+
3
IN-
4
NC
5
VS
6
ENABLE
7
REF
8
GND
9
OUT
10
U12
INA190A2RSW
GND2
0.1
µ
F
C12
GND2
0.002
R82
1
2
3
J42
M20-8770342
GND2
VS2
TP14
TP24
TP34
VS4
VS4
VS4
GND4
GND4
GND4
VS4
GND4
10.0k
R14
REF4
0.1
µ
F
C24
0.1
µ
F
C94
0.1
µ
F
C34
REF4
GND4
0
R54
0
R64
0.1
µ
F
C44
0
R74
GND4
10.0k
R24
0.1
µ
F
C54
GND4
NC
1
NC
2
IN+
3
IN-
4
NC
5
VS
6
ENABLE
7
REF
8
GND
9
OUT
10
U14
INA190A4RSW
GND4
0.1
µ
F
C14
GND4
4
3
2
1
5
V+
V-
U24
TLV6001IDBVR
0.002
R84
1
2
3
J44
M20-8770342
GND4
VS4
J02
IN+
J12
IN-
J04
IN+
J14
IN-
1
2
3
J32
GND2
REF2
REF2
1
2
3
J34
GND4
4
3
2
1
5
V+
V-
U22
TLV6001IDBVR
0
R32
0
R34
TP44
TP42
TP54
TP52
TP64
TP62
TP82
TP84
INA190EVM Schematic and PCB Layout
9
SBOU201A – April 2018 – Revised September 2018
Copyright © 2018, Texas Instruments Incorporated
INA190EVM User's Guide
Figure 2. INA190EVM Schematic - Gain A2 and A4 Panels