TP1
TP2
TP3
VS
VS
VS
GND
GND
GND
VS
GND
10.0k
R1
REF
0.1
µ
F
C2
0.1
µ
F
C9
0.1
µ
F
C3
REF
GND
0
R5
0
R6
0.1
µ
F
C4
0
R7
GND
10.0k
R2
0.1
µ
F
C5
GND
NC
1
NC
2
IN+
3
IN-
4
NC
5
VS
6
ENABLE
7
REF
8
GND
9
OUT
10
U1
INA190A5RSW
GND
0.1
µ
F
C1
GND
1.00k
R8
1
2
3
J4
M20-8770342
GND
VS
TP7
VG
TP15
TP25
TP35
VS5
VS5
VS5
GND5
GND5
GND5
VS5
GND5
10.0k
R15
REF5
0.1
µ
F
C25
0.1
µ
F
C95
0.1
µ
F
C35
REF5
GND5
0
R55
0
R65
0.1
µ
F
C45
0
R75
GND5
10.0k
R25
0.1
µ
F
C55
GND5
NC
1
NC
2
IN+
3
IN-
4
NC
5
VS
6
ENABLE
7
REF
8
GND
9
OUT
10
U15
INA190A5RSW
GND5
0.1
µ
F
C15
GND5
4
3
2
1
5
V+
V-
U25
TLV6001IDBVR
0.002
R85
1
2
3
J45
M20-8770342
GND5
VS5
J0
IN+
J1
IN-
J05
IN+
J15
IN-
1
2
3
J3
GND
1
2
3
J35
GND5
4
3
2
1
5
V+
V-
U2
TLV6001IDBVR
0
R3
0
R35
TP55
TP45
TP65
TP4
TP5
TP6
0
R4
VG
TP8
TP85
INA190EVM Schematic and PCB Layout
10
SBOU201A – April 2018 – Revised September 2018
Copyright © 2018, Texas Instruments Incorporated
INA190EVM User's Guide
Figure 3. INA190EVM Schematic - Gain A5 and Guarding Panels