Texas Instruments GC5328, Manual

Page: 21 / 27

TCK
TDI
TDO
1/f
TCK
t
su(TDI)
t
h(TDI)
t
d(TDO)
T0289-01
t
p(TCKL)
t
p(TCKH)
DAC[15:0]P
I
Q
I
DAC[15:0]N
DACCLK
DACCLKC
t
SKW(DAC)
T0290-01
1/f
CLK(DAC)
GC5328
www.ti.com SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
JTAG SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS PARAMETER MIN MAX UNIT
f
TCK
JTAG clock frequency 50 MHz
t
p(TCKL)
JTAG clock low period 10 ns
t
p(TCKH)
JTAG clock high period 10 ns
t
su(TDI)
Input data setup time before TCK ↑ Valid for TDI and TMS 1 ns
t
h(TDI)
Input data hold time after TCK ↑ Valid for TDI and TMS 6 ns
t
d(TDO)
Output data delay from TCK
↓
8 ns
Figure 14. JTAG Timing Specifictions
TX SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HSTL MODE – DDR ex. DAC5682
f
CLK(DAC)
DAC output clock frequency R
L
= 100 Ω
(1)
300 MHz
t
SKW(DAC)
DACCLK to DAC data R
L
= 100 Ω
(2)
TBD ps
(1) Because the output clock is DDR, the data rate is 2× the f
CLK
rate; f
CLK(DAC)
= (BUC Interp × DPDClk / 2).
(2) t
SKW(DAC)
data clock-to-data is measured during characterization.
Figure 15. TX Timing Specifications (HSTL – DDR)
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