Fullscale
Headroom
PAR
Input
Signal RMS
(DL only)
CFR
Block
Hard
Limiter
7dB
DPD
Expansion
Gain
Output
Signal RMS
(DL only)
Using the Software
4.1.1
Step 1: Signal Setup
1. If the VCXO frequency is not the default 737.28 MHz, select the CLK option (as shown in the following
inset) and input the clock rate in the text window.
In this example, a clock rate of 737.28 MSPS is used. The clock rate must be between 650 and 750
MHz.
2. Input the complex sample rate of your input data if it is different than the default value. The input rate
can be up to the EVM Clock rate divided by 12. For this example, the default value of 61.44 MHz
(737.28 divided by 12) is used.
The GC5325EVM GUI fractionally resamples the signal to match the GC5325 complex input rate of the
EVM Clock divided by 12 (the interface uses an interleaved format for I and Q, so the actual data
transfer rate is 2x).
3. Set the desired Peak to Average Ratio (PAR), Headroom (HR), and TDD% for the CFR block.
Referring to the following diagram, Headroom is the clipping threshold relative to full-scale for the CFR
block and PAR is the RMS level of the input signal below the Headroom. The GC5325EVM GUI
rescales the input signal so as to set the RMS level appropriately. The TDD% value is used to
compensate for the zero time of TDD downlink signals. If the downlink time is 60% of the frame, then
the TDD% must be set to 60.
For this example, the PAR and Headroom settings were kept as the default values of 8 dB and 7 dB.
The PAR and HR settings can be adjusted later after the signal is loaded by selecting the PAR/HR
button.
Figure 7. Signal Levels in the GC5325
–
Definition of HR and PAR
Following the CFR block, a Hard Limiter block that limits the signal to
–
7dB below full-scale. This is to
ensure that the DPD block has 7 dB available for signal expansion and gain adjustment (compensating
for analog gain variation).
10
GC5325 System Evaluation Kit
SLWU063F
–
April 2009
–
Revised April 2011
Copyright
©
2009
–
2011, Texas Instruments Incorporated
