Copyright © 2016, Texas Instruments Incorporated
K2G SoC
DDR3L
MT41K512M8RH
-125:E
DDR3L
MT41K512M8RH
-125:E
DDR3L
MT41K512M8RH
-125:E
DDR3L
MT41K512M8RH
-125:E
DDR3L
MT41K512M8RH
-125:E
D
D
R
3
C
L
K
0
C
E
0
#
R
AS
#
A
0
-A
1
5
BA
0
-BA
2
C
KE
0
#
C
AS
#
R
ESET
#
W
E
#
O
D
T
0
DVDD_DDR
1.35V
CBDQM
CBDQS
CB00-CB03
DQM3
DQS3
DQ24-DQ31
DQM2
DQS2
DQ16-DQ23
DQM1
DQS1
DQ8-DQ15
DQM0
DQS0
DQ0-DQ7
System Description
24
SPRUI65A – April 2016 – Revised January 2018
Copyright © 2016–2018, Texas Instruments Incorporated
K2G General Purpose Evaluation Module (EVMK2G)
3.7
DDR3L Interface
The 66AK2Gxx SoC supports ×36 bit (32-bit data + 4-bit ECC) DDR3L. Four 4-Gbit (512M × 8) DDR3L
chips (MT41K512M8RH-125) from Micron are used to obtain a memory size of 2GByte and one DDR3L
chip is interfaced to the ECC data bus CB00-CB03, CBDQS, and CBDQM. The DDR3L chips are routed
as per Fly-by topology as shown in
Figure 11. DDR3L Interface Block Diagram