Texas Instruments EVMK2G, User Manual, Page: 22 / 83

Y8
CDCM6208
PCIe x1 Connector
K2G SoC
CS2000
CLKOUT
Y7
CLKIN
PCIe_CLK_100MHz
AUDOSC_IN
AUDOSC_OUT
SYSOSC_IN
SYSOSC_OUT
CPTS_TS_COMP
SYSCLOCK
CPTS_REFCLK
DDR_CLK
PCIe_CLK
McASP2AHCLK
24 MHz
250 MHz
24 MHz
100 MHz
100 MHz
Y5
Y6
Copyright © 2016, Texas Instruments Incorporated
System Description
www.ti.com
22 SPRUI65A – April 2016 – Revised January 2018
Submit Documentation Feedback
Copyright © 2016–2018, Texas Instruments Incorporated
K2G General Purpose Evaluation Module (EVMK2G)
3.6 Clock Distribution
The EVMK2G has the following clock sources, crystals, and oscillators.
• 66AK2Gxx SoC clocks (see Figure 9 ):
– Y5: 22.579 MHz Audio clock for SoC
– Y6: 24 MHz System clock to the SoC
– Y7: 12.28 MHz to CS2000
– Y8: 24 MHz Secondary Reference for clock generator
– U62: CDCM clock generator
• Other clocks (see Figure 10 ):
– Y1: 32.768 kHz to AM1802 XDS
– Y2: 24 MHz System clock to AM1802 XDS
– Y3: 25 MHz Clock to BMC Controller
– Y4: 32.768 kHz Real-Time Clock (RTC) to Power Management IC (TPS659118)
– Y9: 25 MHz Clock for Ethernet PHY
– U21: 32.768 kHz Real-Time Clock (RTC) to BMC
– U75: 12.28 MHz Oscillator for audio clocks
Figure 9. 66AK2Gxx SoC Clocks Block Diagram