appear at AUXVCC2 at the switching point defined by SVSMHCTL.SVSMHRRL (or
AUXCTL2.AUX0LVLx). The probability for this event to occur depends on:
a) Operating temperature (higher temperatures increase probability)
b) External AUXVCC2 voltage level (higher voltages increase probability)
c) SVSMHRRL level (lower levels increase probability) defining the switching level in
hardware-controlled mode
d) AUX0LVLx level (lower levels increase probability) defining the switching level in
software-controlled mode (applicable to DVCC only)
Scenario 2: When a battery is connected to DVCC, AUXVCC1 or AUXVCC2 as the first
voltage supply, due to the low internal resistance of the battery a very fast rise time is
seen by the AUXPMM and latch-up current can appear at the connected supply if:
a) Rise times are in the range of 140 kV/s (faster rise times increase probability)
b) Device operates at temperatures of 75 deg C and above (higher temperatures increase
probability)
The latch-up current disappears after complete power cycles of all supply sources.
Workaround
For scenario 1:
- Increase SVSMRRL to a level above maximum external voltage expected on AUXVCC2.
SVSMRRL = 6 or 7 (requires VCORE level of 3) is applicable for AUXVCC2 of up to
maximum voltage, 3.58V, while a lower SVSMRRL setting can be selected if a lower
voltage (e.g. 3.3V) is expected on AUXVCC2.
Or
- Connect all 3 supplies via 3 external diodes to DVCC and realize the switching externally
without using the internal AUXPMM switches. See application report
Three-Phase Electronic Watt-Hour Meter Using the MSP430F471xx"
Or
- Use AUXVCC1 instead of AUXVCC2 for backup supply
For scenario 2:
Limit the supply voltage ramp up time through a series resistor (e.g. 10 Ohm) in the critical
supply path. Side effects such as voltage dips due to high current consumption of the
device need to be considered.
BSL7
BSL Module
Category
Software in ROM
Function
BSL does not start after waking up from LPMx.5
Description
When waking up from LPMx.5 mode, the BSL does not start as it does not clear the Lock
I/O bit (LOCKLPM5 bit in PM5CTL0 register) on start-up.
Workaround
1. Upgrade the device BSL to the latest version (see Creating a Custom Flash-Based
Bootstrap Loader (BSL) Application Note - SLAA450 for more details)
OR
2. Do not use LOCKLPM5 bit (LPMx.5) if the BSL is used but cannot be upgraded.
BSL14
BSL Module
Category
Software in ROM
Advisory Descriptions
8
MSP430F6746 Microcontroller
SLAZ487AD – DECEMBER 2012 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
