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DM388
DDR CORE SUPPLY
DDR0
GPMC
DEVOSC_MXI
DEVOSC_MXO
AUXOSC_MXI
AUXOSC_MXO
CLKIN32
JTAG
RESET OUT
PORn
HD DAC
SUPPLY
CORE SUPPLY
I2C0
TVOUT
EMAC0
USB0.1
UART0, 1, 2
MMC1
HDMI
I2C 2,3
SPI0, 1
McASP1
CS12
CAM
GPIOs
3V3 I/O SUPPLY
MMC0, McASP0,
UART2
HDDAC
VIN
McASP0
McASP1
MMC2
PCIe
UART0
UART2
Wi-Fi Module
WL1837
Level
Translators
Board-to-Board Termination
DDR Power
TPS51216
2 x 4 Gb
DDR3 X 16
MT41K256M16TW
2 Gb
NAND Flash
MT29F2G16ABAEAWP:E
Bo
a
rd
-t
o
-Bo
a
rd
C
o
n
n
e
ct
o
r
Bo
a
rd
-to
-Bo
a
rd
C
o
n
n
e
ct
o
r
LDO
TPS71711DCKR
PMIC
TPS6591133
DELAYED 3.3
5 V, 3.3
PWRON
3.3 V
RESET IN
nRESPWRON2
DDR PGOOD
20 MHZ
27 MHZ
32.768 KHz
OSC
MUXER
CAM / UART2
UART2
RTS &
CTS
CAM CLK
& FLD
1.1 V
SPI1
CHIP ANTENNA
5 V
Copyright © 2016, Texas Instruments Incorporated
Block Diagram
14
SPRUIC7 – December 2016
Copyright © 2016, Texas Instruments Incorporated
TMDSCSK388 Module
2.2
Block Diagram
shows the TMDSCSK388 block diagram.
Figure 2-1. TMDSCSK388 Block Diagram