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DM388 Processor
DDR3
MT41K256M16TW
DDR3
MT41K256M16TW
DDR0_DQ[0:15]
DDR0_DQS[0:1]
DDR0_DQSn[0:1]
DDR0_DQM[0:1]
DDR0_DQ[16:31]
DDR0_DQS[2:3]
DDR0_DQSn[2:3]
DDR0_DQM[2:3]
DDR0_CLKn
DDR0_CLK
DDR0_BA[0:2]
DDR0_A[0:14]
DDR0_CASn
DDR0_WEn
DDR0_CS0n
DDR0_CLKe
DDR0_RST
DDR0_RASn
DDR0_ODT
1.5 V
DVDD_DDR
Copyright © 2016, Texas Instruments Incorporated
DDR3 Interface
20
SPRUIC7 – December 2016
Copyright © 2016, Texas Instruments Incorporated
TMDSCSK388 Module Interface Details
3.3
DDR3 Interface
The DM388 processor supports 32-bit data DDR2, DDR3, DDR3L, and SDRAM interfaces. The two 4-Gb
(256M x16) DDR3L chips (MT41K256M16TW-107 [backward compatible to DDR3]) from Micron are used
to obtain a memory size of 1 GB. The DDR3L chips are routed using Fly-by topology, shown in
Figure 3-3. DDR3 Bank0 Interface