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1.1
Block Diagram
SW003
System Clock
Data Format
SW004
Clock Mode
JP001
X’tal Frequency
System Clock
DIR1703
24.576MHz
PCM3052A
(Slave Only)
LPF
2 Vrms
LPF
LPF
R-ch
LPF
JP107
JP105
JP106
DIT4096
SW005
System Clock
Data Format
SW006
74HCT244
OPT. IN
COAX. IN
S/PDIF Input
SW001
SW051
1/2 Vrms
S/PDIF Output
R-ch
OPT. OUT
COAX. OUT
DAC Output
ADC Input
MIC Input
Channel Status
L-ch
10/20 mVrms
L-ch
Block Diagram
Figure 1-1. DEM-DAI3052A Block Diagram
Description
6
SLEU079 – September 2006
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