Parallel Control
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4.2
DC_CS Signals
The DC_CS signal is used as a board select for the EVM. It is an active low signal that controls the output
enable bit on the SN74LVC16245 and, in conjunction with the external logic, is used to create the CS
signal for the DAC8728. The user selects one of the three possible addresses using JP10. By default, the
DC_CS signal is set to the 2Y1 output of the SN74LVC139. When accessing the parallel bus, if the
appropriate address is not selected to pull the DC_CS signal on the EVM low, then the SN74LVC16245
(U10) is not active and the DAC8728 does not see the activity on the bus.
4.3
CS Signal
The CS signal is formed from the output of the logic circuit. The DAC8728 uses the CS signal in
combination with the R/W signal to enable the input and output buffers. When the CS signal is high, the
data input lines to the DAC8728 are HI-Z. On the falling edge of CS, data on the parallel bus are passed
into the DAC8728; on the rising edge, data are latched into the appropriate register.
4.4
R/W Signal
The R/W signal is located on the 1Y1 output of the SN74LVC139 (U7). During read and write commands
to the EVM, the appropriate address must be selected to set the R/W bit either high for a read or low for a
write. The DAC8728 uses the R/W signal to enable and disable the input and output buffers inside the
chip. When the R/W signal is high and CS is low, the output buffers are activated sending the register data
from the DAC8728 to the parallel bus. When R/W is low and CS is low, the input buffers are activated and
the data present on the bus are passed into the DAC.
4.5
LATCH, LATCH_CTRL Signals
The LATCH_CTRL signal is located on the 1Y0 output of the SN74LVC139 (U7). The LATCH_CTRL
signal is logic ORed with the WE signal to create the LATCH signal that is used to control the CLK input to
the SN74LVC374 on the EVM. During the first stage of a read or write operation, the LATCH_CTRL bit is
taken low while the DAC8728 register address is placed on the first five bits of the parallel data bus. When
the WE signal goes low during this write, the LATCH signal also transitions low. When the WE signal
returns high, the LATCH signal also goes high, which then locks the DAC8728 register address to the
A0–A4 address bus on the DAC8728.
4.6
LDAC, LDAC_CTRL, EXT_LDAC Signals
The LDAC signal is driven by the external logic and is used to update the DAC outputs with the data
present in the V
OUT
registers. This signal is active low and can be triggered synchronously or
asynchronously. The LDAC_CTRL signal is located on the 2Y3 output of the SN74LVC139 (U7). The
EXT_LDAC signal is driven from pin J1.17 on the parallel control header.
4.7
CLR Signal
The CLR signal is located on the 1Y2 output of the SN74LVC139 (U7). When set low, the DAC analog
outputs are tied to GND through an internal 20k
Ω
resistor and the output buffers are disabled. For normal
operation, this signal must remain high.
4.8
RST Signal
The RST signal is located on the 1Y3 output of the SN74LVC139 (U7). When set low, the device is in a
full hardware reset. The analog outputs are connected to GND through the internal low impedance, while
the input registers and OFFSET and DAC latches are loaded with the value defined by the RSTSEL pin
on the DAC8728. The gain registers and zero registers are loaded with the respective default values and
the communication bus is disabled. For normal operation, the RST signal must remain high.
8
DAC8728EVM
SBAU161 – February 2010
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