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4
Circuit Description
4.1
Input Clocks
4.2
Input Data
Circuit Description
Table 1. DAC5687 EVM Parts List (continued)
Bill of Material For DAC5687
Value
Qty. Part Number
Vendor
Ref Des
Not Installed
CDCV304
1
CDCV304PW
TI
U5
SN74HC241
1
SN74HC241DW
TI
U4
SN74HCT14
2
SN74HCT14PWR
TI
U2, U3
Transformer
2
T4-1-KK8
Mini-circuits
T1, T2
Transformer
2
TCM4-1W
Mini-circuits
T3, T4
Transformer
1
T1-6T-KK81
Mini-circuits
T5
DB25F-RA
1
745536-2
AMP
J1
Switch
1
EVQ-PJX04M
Panasonic
S1
This chapter describes the circit functions of the DAC5687 EVM.
The initial configuration of this EVM provides transformer-coupled differential clocks from single-ended
input sources. With the EVM configured for PLL clock mode, a 1-V
PP
, 0-V offset, 50% duty cycle external
square wave is applied to SMA connector J3 to be used as the data input rate clock. The signal is
converted to a differential clock by transformer T3 and provides the CLK1 and CLK1C inputs to the
DAC5687 device. This input represents a 50-
Ω
load to the source. In order to preserve the specified
performance of the DAC5687 converter, the clock source should feature very low jitter. Using a clock with
a 50% duty cycle gives optimum dynamic performance.
With the EVM configured for external clock mode, a 1-V
PP
, 0-V offset, 50% duty cycle external square
wave is applied to SMA connector J4 to be used as the DAC sample clock. The signal is converted to a
differential clock by transformer T4 and provides the CLK2 and CLK2C inputs to the DAC5687 device.
This input represents a 50-
Ω
load to the source. In order to preserve the specified performance of the
DAC5687 converter, the clock source should feature low jitter. Using a clock with a 50% duty cycle gives
optimum dynamic performance.
The DAC5687 EVM can accept 1.8-V or 3.3-V CMOS logic level data inputs through the 34-pin headers
J13 and J14 per
and
. The board provides options for 50-
Ω
termination to ground and
series dampening resistors to minimize digital ringing and switching noise. Jumper W2 determines which
voltage level is to be used for the logic inputs.
Table 2. Input Connector J13 (Data A Bus)
Pin
Description
Pin
Description
1
CMOS data bit 15 (MSB)
18
GND
2
GND
19
CMOS data bit 6
3
CMOS data bit 14
20
GND
4
GND
21
CMOS data bit 5
5
CMOS data bit 13
22
GND
6
GND
23
CMOS data bit 4
7
CMOS data bit 12
24
GND
8
GND
25
CMOS data bit 3
9
CMOS data bit 11
26
GND
10
GND
27
CMOS data bit 2
22
DAC5687 EVM
SLWU017B – APRIL 2005 – Revised March 2007