Texas Instruments DAC5652AEVM, User Manual

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Schematic Diagram
5 SLAU773 – May 2018
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DAC5652AEVM User's Guide
3.2 Input Data
The DAC5652A EVM can 3.3-V CMOS logic level data inputs through the 80-pin headers J9 in
Table 1 . The user can provide series dampening resistors to minimize digital ringing and switching noise if
required. The default values are 0 Ω .
Table 1. Input Connector J9
J9 Pin Number Description J9 Pin Number Description
9 DAC A data bit 9 (MSB) 55 DAC B data bit 9 (MSB)
10 Ground 56 Ground
11 DAC A data bit 8 57 DAC B data bit 8
12 Ground 58 Ground
13 DAC A data bit 7 59 DAC B data bit 7
14 Ground 60 Ground
15 DAC A data bit 6 61 DAC B data bit 6
16 Ground 62 Ground
17 DAC A data bit 5 63 DAC B data bit 5
18 Ground 64 Ground
19 DAC A data bit 4 65 DAC B data bit 4
20 Ground 66 Ground
21 DAC A data bit 3 67 DAC B data bit 3
22 Ground 68 Ground
23 DAC A data bit 2 69 DAC B data bit 2
24 Ground 70 Ground
25 DAC A data bit 1 71 DAC B data bit 1
26 Ground 72 Ground
27 DAC A data bit 0 (LSB) 73 DAC B data bit 0 (LSB)
28 Ground 74 Ground
3.2.1 Output Signal
The DAC5652AEVM can be configured to drive a doubly terminated 50- Ω cable or provide unbuffered
differential outputs.
3.2.2 Transformer-Coupled Signal Output
The factory-set configuration of the demonstration board provides the user with a single-ended output
signals from channel A and B of the DAC at SMA connector J1 and J4. The DAC5652A is configured to
drive a doubly terminated 50-
Ω cable using a 4:1 impedance ratio transformer and the center tap of T1
and T2 connected to ground. When using a 1:1 impedance ratio transformer, configure the EVM per
Table 2 .
Table 2. Transformer Output Configuration
Configuration Components Installed Components Not Installed
1:1 Impedance ratio
transformer
R3 − R5, R13, R15,R16 T1, T2 R1, R8, C1, C9
4:1 Impedance ratio
transformer
R4 (100), R5 (100), R15 (100), R16 (100), T1 (4:1), T2 (4:1) R1, R3, R13, R9, R18, C1, C9