Register Descriptions
1348
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
18.5.38 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-
USBRXCSRH[15])
The USB receive control and status endpoint
n
high 8-bit register (USBCSRL[
n
]) provides additional
control and status bits for transfers through the currently selected receive endpoint.
For the specific offset for each register see
.
Mode(s):
OTG A or Host
OTG B or Device
The USBCSRH[
n
] registers in OTG A/Host mode are shown in
and described in
Figure 18-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in OTG
A/Host Mode
7
6
5
4
3
2
1
0
AUTOCL
AUTORQ
DMAEN
PIDERR
DMAMOD
DTWE
DT
Reserved
W1C-0
R/W-0
R/W-0
R-0
R/W-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; -
n
= value after reset
Table 18-51. USB Control and Status Endpoint n High Register (USBCSRH[n])
in OTG A/Host Mode Field Descriptions
Bit
Field
Value
Description
7
AUTOCL
Auto Clear
0
No effect
1
Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[
n
] bytes has been
unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. Care must be taken when using
μ
DMA to unload the receive FIFO
as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in
the USBRXMAXP[
n
] register, see
6
AUTORQ
Auto Request
Note:
This bit is automatically cleared when a short packet is received.
0
No effect
1
Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared.
5
DMAEN
DMA Request Enable
Note:
Three TX and three RX endpoints can be connected to the
μ
DMA module. If this bit is set for a
particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
0
Disables the
μ
DMA request for the receive endpoint.
1
Enables the
μ
DMA request for the receive endpoint.
4
PIDERR
PID Error. This bit is ignored in bulk or interrupt transactions.
0
No error
1
Indicates a PID error in the received packet of an isochronous transaction.
3
DMAMOD
DMAMOD
Note:
This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
0
An interrupt is generated after every
μ
DMA packet transfer.
1
An interrupt is generated only after the entire
μ
DMA transfer is complete.
2
DTWE
Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
0
The DT bit cannot be written.
1
Enables the current state of the receive endpoint data to be written (see DT bit).
1
DT
Data Toggle. When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any
value written to this bit is ignored. Care should be taken when writing to this bit as it should only be
changed to RESET the receive endpoint.
0
Reserved
0
Reserved
