background image

Electrical Characteristics

(Continued)

A

V

= +10, V

CC

=

±

5V, R

L

= 100

, R

f

= 1k

, R

g

= 182

, V

g

= +2V; unless specified

Symbol

Parameter

Conditions

Typ

Max/Min (Note 2)

Units

IB

Input Bias Current (Note 5)

12

<

61

<

28

<

28

µA

DIB

Average Temperature Doefficient

100

<

415

-

<

165

nA/˚C

IOS

Input Offset Current

0.5

<

4

<

2

<

2

µA

DIOS

Average Temperature Coefficient

5

<

40

-

<

20

nA/˚C

PSS

Power Supply Sensitivity

Output Referred DC

10

<

28

<

28

<

28

mV/V

CMRR

Common Mode Rejection Ratio

Input Referred

70

>

59

>

59

>

59

dB

ICC

Supply Current (Note 5)

No Load

28

<

38

<

38

<

38

mA

RIN

V

IN

Signal Input

Resistance

200

>

50

>

100

>

100

k

CIN

Capacitance

1

<

2

<

2

<

2

pF

DMIR

V

IN

Differential Voltage Range

R

g

= 182

only

±

280

±

250

±

250

±

210

mV

CMIR

Common Mode Voltage Range

±

2.2

>

±

1.4

>

±

2

>

±

2

V

RINC

V

g

Control Input

Resistance

750

>

535

>

600

>

600

CINC

Capacitance

1

<

2

<

2

<

2

pF

VGHI

V

g

Input Voltage

For Max Gain

1.6

<

2

<

2

<

2

k

VGLO

For Min Gain

0.4

>

0

>

0

>

0

V

RO

Output Impedance

At DC

0.1

<

0.3

<

0.2

<

0.2

VO

Output Voltage Range

No Load

±

3.5

>

±

3

>

±

3.2

>

±

3.2

V

IO

Output Current

±

60

>

±

35

>

±

50

>

±

50

mA

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.

Note 3: Measured at A

VMAX

= 10, V

g

= +2V

Note 4: Differential gain and phase are measured at: A

V

= +20, V

g

= +2V, R

L

= 150

, R

f

= 2k

, R

g

= 182

, equivalent video signal of 0-100 IRE with 40 IRE

PP

at 3.58 MHz.

Note 5: AJ-level: spec. is 100% tested at +25˚C.

CLC520

www.national.com

4

Summary of Contents for CLC520

Page 1: ...CLC520 CLC520 Amplifier with Voltage Controlled Gain AGC Amp Literature Number SNOS861C...

Page 2: ...ess than 0dB The gain control bandwidth of 100MHz is superb for AGC ALC loop stabilization And since the gain is minimum with a zero volt input and maximum with a 2 volt input driving the control inpu...

Page 3: ...n Package Temperature Range Industrial Part Number Package Marking NSC Drawing 14 pin plastic DIP 40 C to 85 C CLC520AJP CLC520AJP N14A 14 pin plastic SOIC 40 C to 85 C CLC520AJE CLC520AJE M14A CLC520...

Page 4: ...z 3dB Bandwidth VOUT 0 5VPP SBWC Gain Control Channel VIN 0 2V Vg 1VDC 100 80 80 80 MHz Gain Flatness VOUT 0 5VPP GFPL Peaking 0 1MHz to 30MHz 0 0 4 0 3 0 4 dB GFPH Peaking 0 1MHz to 20MHz 0 0 7 0 5 0...

Page 5: ...600 600 CINC Capacitance 1 2 2 2 pF VGHI Vg Input Voltage For Max Gain 1 6 2 2 2 k VGLO For Min Gain 0 4 0 0 0 V RO Output Impedance At DC 0 1 0 3 0 2 0 2 VO Output Voltage Range No Load 3 5 3 3 2 3...

Page 6: ...Rf 1k Rg 182 Vg 2V Frequency Response AVMAX 2 Frequency Response AVMAX 10 01275630 01275616 Frequency Response AVMAX 100 Large Signal Frequency Response 01275619 01275621 Small Signal Gain vs Rf 2nd...

Page 7: ...RL 100 Rf 1k Rg 182 Vg 2V Continued 3rd Harmonic Distortion 2nd and 3rd Harmonic Distortion vs Vg 01275602 01275603 Gain vs Vg Gain vs Vg 01275640 01275639 Large and Small Signal Pulse Response Settli...

Page 8: ...Rf 1k Rg 182 Vg 2V Continued Settling Time Vg 1 2V Long Term Settling Time 01275614 01275615 Settling Time vs Capacitive Load AVMAX 10 Gain Control Settling Time 01275604 01275617 Gain Control Channe...

Page 9: ...C 5V RL 100 Rf 1k Rg 182 Vg 2V Continued Differential Gain and Phase PSRR 01275643 01275606 Output Noise vs Vg Linearity Vg 0 6V to 1 6V 01275622 01275644 Linearity Vg 0 75V to 1 4V Linearity Vg 0 9V...

Page 10: ...e net gain control port input impedance is 50 set by the parallel combination of R1 and the 750 input impedance of pin 2 of the CLC520 Rf is set to the standard value 1k and Rg sets the maximum voltag...

Page 11: ...a similar fash ion Capacitance to ground should be minimized by remov ing the ground plane from under the resistor of Rg Parasitic or load capacitance directly on the output pin 10 degrades phase mar...

Page 12: ...ffer non inverting input is grounded The core noise is already output referred and is 37nV at Vg 1 1 AVMAX 2 and approaches zero as A goes to 0 or AVMAX Summing the noise power for each term gives the...

Page 13: ...Physical Dimensions inches millimeters unless otherwise noted 14 Pin MDIP NS Package Number N14A 14 Pin SOIC NS Package Number M14A CLC520 www national com 12...

Page 14: ...e failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Corporation Americas Email sup...

Page 15: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

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