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CLC520
Amplifier with Voltage Controlled Gain, AGC +Amp

General Description

The CLC520 is a wideband DC-coupled amplifier with volt-
age controlled gain (AGC). The amplifier has a high imped-
ance, differential signal input; a high bandwidth, gain control
input; and a single-ended voltage output. Signal channel
performance is outstanding with 160MHz small signal band-
width, 0.5 degree linear phase deviation (to 60MHz) and
0.04% signal nonlinearity at 4V

PP

output.

Gain control is very flexible and easy to use. Maximum gain
may be set over a nominal range of 2 to 100 with one
external resistor. In addition, the gain control input provides
more than 40dB of voltage controlled gain adjustment from
the maximum gain setting. For example, a CLC520 may be
set for a maximum gain of 2 (or 6dB) for a voltage controlled
gain range from 40dB to less than 34dB. Alternatively, the
CLC520 could be set for a maximum gain of 100 or (40dB)
for a voltage controlled gain range from 40dB to less than
0dB.

The gain control bandwidth of 100MHz is superb for AGC/
ALC loop stabilization. And since the gain is minimum with a
zero volt input and maximum with a +2 volt input, driving the
control input is easy.

Finally, the CLC520 differential inputs, and ground refer-
enced voltage output take the trouble out of designing
DC-coupled AGC circuits for display normalizers; signal lev-
eling automatic circuits; etc.

Enhanced Solutions (Military/Aerospace)

SMD Number: 5962-91694

Space level versions also available.

For more information, visit http://www.national.com/mil

Features

n

160MHz, −3dB bandwidth

n

2000V/µsec slew rate

n

0.04% signal nonlinearity at 4V

PP

output

n

−43dB feedthrough at 30MHz

n

User adjustable gain range

n

Differential voltage input and single-ended voltage
output

Applications

n

Wide bandwidth AGC systems

n

Automatic signal leveling

n

Video signal processing

n

Voltage controlled filters

n

Differential amplifier

n

Amplitude modulation

Gain vs. V

g

01275640

01275639

Gain vs. V

g

Connection Diagram

01275629

Pinout

DIP & SOIC

May 2001

CLC520

Amplifier

with

V

oltage

Controlled

Gain,

AGC

+Amp

© 2001 National Semiconductor Corporation

DS012756

www.national.com

Summary of Contents for CLC520

Page 1: ...CLC520 CLC520 Amplifier with Voltage Controlled Gain AGC Amp Literature Number SNOS861C...

Page 2: ...ess than 0dB The gain control bandwidth of 100MHz is superb for AGC ALC loop stabilization And since the gain is minimum with a zero volt input and maximum with a 2 volt input driving the control inpu...

Page 3: ...n Package Temperature Range Industrial Part Number Package Marking NSC Drawing 14 pin plastic DIP 40 C to 85 C CLC520AJP CLC520AJP N14A 14 pin plastic SOIC 40 C to 85 C CLC520AJE CLC520AJE M14A CLC520...

Page 4: ...z 3dB Bandwidth VOUT 0 5VPP SBWC Gain Control Channel VIN 0 2V Vg 1VDC 100 80 80 80 MHz Gain Flatness VOUT 0 5VPP GFPL Peaking 0 1MHz to 30MHz 0 0 4 0 3 0 4 dB GFPH Peaking 0 1MHz to 20MHz 0 0 7 0 5 0...

Page 5: ...600 600 CINC Capacitance 1 2 2 2 pF VGHI Vg Input Voltage For Max Gain 1 6 2 2 2 k VGLO For Min Gain 0 4 0 0 0 V RO Output Impedance At DC 0 1 0 3 0 2 0 2 VO Output Voltage Range No Load 3 5 3 3 2 3...

Page 6: ...Rf 1k Rg 182 Vg 2V Frequency Response AVMAX 2 Frequency Response AVMAX 10 01275630 01275616 Frequency Response AVMAX 100 Large Signal Frequency Response 01275619 01275621 Small Signal Gain vs Rf 2nd...

Page 7: ...RL 100 Rf 1k Rg 182 Vg 2V Continued 3rd Harmonic Distortion 2nd and 3rd Harmonic Distortion vs Vg 01275602 01275603 Gain vs Vg Gain vs Vg 01275640 01275639 Large and Small Signal Pulse Response Settli...

Page 8: ...Rf 1k Rg 182 Vg 2V Continued Settling Time Vg 1 2V Long Term Settling Time 01275614 01275615 Settling Time vs Capacitive Load AVMAX 10 Gain Control Settling Time 01275604 01275617 Gain Control Channe...

Page 9: ...C 5V RL 100 Rf 1k Rg 182 Vg 2V Continued Differential Gain and Phase PSRR 01275643 01275606 Output Noise vs Vg Linearity Vg 0 6V to 1 6V 01275622 01275644 Linearity Vg 0 75V to 1 4V Linearity Vg 0 9V...

Page 10: ...e net gain control port input impedance is 50 set by the parallel combination of R1 and the 750 input impedance of pin 2 of the CLC520 Rf is set to the standard value 1k and Rg sets the maximum voltag...

Page 11: ...a similar fash ion Capacitance to ground should be minimized by remov ing the ground plane from under the resistor of Rg Parasitic or load capacitance directly on the output pin 10 degrades phase mar...

Page 12: ...ffer non inverting input is grounded The core noise is already output referred and is 37nV at Vg 1 1 AVMAX 2 and approaches zero as A goes to 0 or AVMAX Summing the noise power for each term gives the...

Page 13: ...Physical Dimensions inches millimeters unless otherwise noted 14 Pin MDIP NS Package Number N14A 14 Pin SOIC NS Package Number M14A CLC520 www national com 12...

Page 14: ...e failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Corporation Americas Email sup...

Page 15: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

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