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Introduction
Introduction
The CDCM7005 is a high-performance, low phase noise and low skew clock
synchronizer that synchronizes an on-board voltage controlled crystal
oscillator (VC(X)O) frequency to an external reference clock. The device
operates up to 2.2 GHz. The PLL loop bandwidth and damping factor can be
adjusted to meet different system requirements by selecting the external
VC(X)O, loop filter components, frequency for PFD, and charge pump current.
Each of the five differential LVPECL and five LVCMOS pair outputs can be
programmed by a serial peripheral interface (SPI). The SPI allows individual
control of the frequency and enable/disable state of each output. As the
system requires external components like a loop filter and VC(X)O, this EVM
provides an easy method to evaluate and modify the performance and
parameters of the clock system in conjunction with the specific customer
application. Loop bandwidth can be selected as low as 10 Hz or less, allowing
the device to clean the system’s clock jitter.
In non PLL mode, the CDCM7005 can be used as a simple LVPECL or
LVCMOS buffer with divider options.
Topic
Page
1.1
CDCM7005 Functional Block Diagram
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Chapter 1
Summary of Contents for CDCM7005
Page 25: ...Parts List 6 6 Figure 6 2 Component View and Silkscreen Bottom View...
Page 26: ...Parts List 6 7 Parts List Board Layout and Schematics Figure 6 3 Top Layer View...
Page 27: ...Parts List 6 8 Figure 6 4 Bottom Layer View...
Page 28: ...Parts List 6 9 Parts List Board Layout and Schematics Figure 6 5 Ground Plane View...