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Hardware Configuration

3-3

EVM Hardware

3.2.3 Programming Interfaces (J30, J31)

The SPI of the device is used for writing to the control register of the device.
It consists of three control lines CTRL_CLK, CTRL_DATA, and CTRL_LE.
There are four 30-bit wide RAM registers, which can be addressed by the two
LSBs of a transferred word. Every transmitted word must have 32 bits, starting
with MSB. After supplying power or activating the power-down mode, the
registers are loaded with the device default values internally (see the
CDCM7005 data sheet, SCAS793). However, if specific register settings are
required for any applications, there are two ways to program the device
externally:

-

Connect the parallel port cable to the PC and EVM parallel port. This
needs control S/W (see Chapter 4).

3.2.4 Loop Filter (J32

J34)

The loop filter is one of the key elements determining the loop bandwidth of
the PLL. The loop filter converts the charge pump current into the control
voltage for the voltage controlled oscillator. The phase difference between the
input clocks of the phase frequency detector determines the width of the
charge pump output current pulses. These high frequency pulses are
transformed into a voltage to control the oscillator.

Basically, three types of loop filters are implemented on the EVM.

-

Passive loop filter

-

External active loop filter using an external low-noise OPA.

Filter types can be selected by soldering bridges J32

J34, see Table 3

1.

Control voltage of the VC(X)O can be measured at J9 or TP1. If an external
OPA is used, it needs to be switched on by connecting J34. For example,
passive filter operation is provided when pads 1 and 3 of J33 are solder bridged
and pads 1 and 3 of J32 are solder bridged.

Default setting:  Passive Loop Filter

Table 3

1. Filter Configurations

Bridge

Passive Filter

Active With An External OPA

J33

1

3

1

2

J34

Open

Closed

J32

1

3

1

2

3.2.5 High-Speed Outputs and Inputs (J1

J4, J6

J11, J13, J14, J22, and J23)

The CDCM7005 drives five differential LVPECL outputs. All PECL outputs are
ac-coupled and terminated with 150 

 to GND. This is in contrast to typical

LVPECL termination, which requires V

CC 

 2 V as termination voltage. The

reason is to simplify the power supply scheme. The device output’s trace
impedance is 50 

 and traces are matched in length. All outputs have options

for pullup and pulldown resistors.

Summary of Contents for CDCM7005

Page 1: ...CDCM7005 QFN Package Evaluation Module Manual HPA High Speed Communications 2005 Clock Drivers User s Guide SCAU015...

Page 2: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Page 4: ...inty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 45 C The EVM is designed to operate p...

Page 5: ...tion From Texas Instruments CDCM7005 Data Sheet SCAS793 Texas Instruments FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio f...

Page 6: ...2 5 High Speed Outputs and Inputs J1 J4 J6 J11 J13 J14 J22 and J23 3 3 3 2 6 VCXO Inputs and Outputs J16 J18 3 4 3 2 7 AC Coupling at PRI_REF C1 R4 R6 and SEC_REF C5 R13 R15 3 4 4 Serial Peripheral I...

Page 7: ...ion 5 2 5 2 CDCM7005 With an External Active Loop Filter Using OPA341 5 3 6 1 Component View and Silkscreen Top Side 6 5 6 2 Component View and Silkscreen Bottom Side 6 6 6 3 Top Layer View 6 7 6 4 Bo...

Page 8: ...LVPECL and five LVCMOS pair outputs can be programmed by a serial peripheral interface SPI The SPI allows individual control of the frequency and enable disable state of each output As the system requ...

Page 9: ...LV PECL LV CMOS Y1B Y1A LV CMOS LV PECL LV CMOS Y2B Y2A LV CMOS LV PECL LV CMOS Y3B Y3A LV CMOS LV PECL LV CMOS Y4B Y4A LV CMOS LV PECL SPI LOGIC Manual Automatic CLK Select Current Reference Referenc...

Page 10: ...he VC X O frequency If REF_SEL is set to 1 then PRI_REF is selected If REF_SEL is set to 0 then SEC_REF is selected This selection can be realized via J26 header 1 and 2 is high header 2 and 3 is low...

Page 11: ...3 1 EVM Hardware EVM Hardware This chapter discusses the EVM hardware Topic Page 3 1 Board View and Connector Location 3 2 3 2 Hardware Configuration 3 2 Chapter 3...

Page 12: ...all current sources are switched off all outputs are switched into 3 state and all dividers M N and P are reset to default Push SW2 to enter the reset mode of the device The charge pump CP is switched...

Page 13: ...etector determines the width of the charge pump output current pulses These high frequency pulses are transformed into a voltage to control the oscillator Basically three types of loop filters are imp...

Page 14: ...X O in order to complete the PLL loop The VC X O adjusts the frequency and phase depending on the control voltage level coming from the loop filter and provide the input clock to the LVPECL block Anot...

Page 15: ...heral Interface SPI Software Serial Peripheral Interface SPI Software This chapter discusses the serial peripheral interface software Topic Page 4 1 Functional Description 4 2 4 2 Software Installatio...

Page 16: ...rule of thumb here are some examples Use of active loop filter Change of divider ratio or disable of certain LVPECL LVCMOS outputs Select between LVPECL or LVCMOS output Change of phase offset Delay M...

Page 17: ...5 1 Application Circuit Diagram Application Circuit Diagram This chapter discusses the application circuit diagram Topic Page 5 1 Application Circuit Diagram 5 2 Chapter 5...

Page 18: ...he overall loop stability R1 C1 and C2 generate the dominant pole of the system A second pole is introduced by R2 and C3 Figure 5 1 CDCM7005 With a Passive Loop Filter Configuration SPI PECL_OUT_B PEC...

Page 19: ...ter Using OPA341 SPI PECL_OUT_B PECL_OUT V_CTRL VC X O CP_OUT CTRL_LE CTRL_DATA CTRL_CLK CDCM7005 PLL_LOCK STATUS_VC X O STATUS_REF Vcc Low Pass Filter Vcc InP InN Out OPA341 R 82 R 82 R 150 R 150 10...

Page 20: ...out and Schematics Parts List Board Layout and Schematics This chapter contains the parts list board layout and schematics for the CDCM7005 EVM Topic Page 6 1 Parts List 6 2 6 2 Board Layout 6 4 6 3 S...

Page 21: ...smd_cap_0402 NU 1 1 pF NU Rohm MCH155A1R1CK 10 1 C24 smd_cap_0402 22 pF Panasonic ECJ 0EC1H220J 11 1 C25 smd_cap_0402 NU 1 pF NU Rohm MCH155A1R1CK 12 7 C27 C29 C75 C76 C79 C80 smd_cap_0805 0 1 F Pana...

Page 22: ...der 2 pos 0 1 ctr 33 2 J21 J20 smd_bridge_0402 SMD3P_BRIDGE Panasonic ERJ 2GE0R00X 34 3 J24 J28 J29 jumper2 HDR2 Header 2 pos 0 1 ctr 35 1 J30 dcon25m PARALLEL PORT SPC Technology DB 25P PCB 36 1 J31...

Page 23: ...es_0402 NU 100 Panasonic ERJ 2RKF1000X 59 4 R51 R64 R66 R67 smd_res_0402 100 k Panasonic ERJ 2RKF1003X 60 1 R52 smd_res_0402 160 Panasonic ERJ 2RKF1002X 61 2 R53 R72 smd_res_0402 4 7 k Panasonic ERJ 2...

Page 24: ...Parts List 6 5 Parts List Board Layout and Schematics 6 2 Board Layout Figure 6 1 Component View and Silkscreen Top View...

Page 25: ...Parts List 6 6 Figure 6 2 Component View and Silkscreen Bottom View...

Page 26: ...Parts List 6 7 Parts List Board Layout and Schematics Figure 6 3 Top Layer View...

Page 27: ...Parts List 6 8 Figure 6 4 Bottom Layer View...

Page 28: ...Parts List 6 9 Parts List Board Layout and Schematics Figure 6 5 Ground Plane View...

Page 29: ...Parts List 6 10 Figure 6 6 Power Layer View 6 3 Schematics The following pages contain the schematics for the CDCM7005 QFN package...

Page 30: ...1 2 C53 10n 1 2 C66 10n 1 2 C38 100n 1 2 C59 2 2n 1 2 C57 10n 1 2 C46 10n 1 2 C37 10uF 1 2 C65 10uF 1 2 C48 22uF 1 2 L5 75 OHM 100MHZ 1 2 C52 33n 1 2 P1 PW R_IN 1 1 C60 2 2n 1 2 C64 100P 1 2 C67 2 2n...

Page 31: ...5 Tuesday April 26 2005 SW1 R 54 750 1 2 J25 1 2 3 R 57 10K 1 2 D3 Amber 1 2 D2 Amber 1 2 J29 1 2 R59 10K 1 2 D1 Amber 1 2 U2 CDCM7005 Y2B 8 Y2A 7 VCC_CP 33 AVCC 32 NC 34 Y3B 12 Y3A 11 REF_SEL 35 AVCC...

Page 32: ...day April 26 2005 V CHECK Passive Filter Default Setting short pin 1 3 on J3 2 J33 Active Filter w External Op Amp short pin 1 2 on J32 J33 J34 J33 2 1 3 C30 22uF 1 2 R52 160 1 2 R73 180 1 2 C75 1uF 1...

Page 33: ...3 10n 1 2 R92 0 ohm 1 2 C20 1uF 1 2 C4 10n 1 2 R22 NU 100 1 2 R23 150 1 2 R28 NU 0 ohm 1 2 R14 150 1 2 J14 NU_SMA 1 2 3 R40 62 1 2 R33 0 ohm 1 2 R34 0 ohm 1 2 R88 0 ohm 1 2 J19 1 2 C 26 10n 1 2 VCXO1...

Page 34: ...CDCM7005EVM_QFN SCH A CDCM7005_QFN Evaluation Module B 55 Tuesday April 26 2005 R64 100K 1 2 C73 100P 1 2 R 66 100K 1 2 J30 PARALLEL PORT 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25...

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