3.1.9 BoosterPack Sites
The F28003x LaunchPad features two fully independent BoosterPack XL connectors. Both BoosterPack sites
1 and 2 are compliant with the BoosterPack standard. To expand the functions available to the user on this
LaunchPad, some signals are also routed to alternate locations on the board. These alternate routes can be
selected by manipulating the onboard switches or by adding / removing 0 Ω resistors. This is described in
.
The GPIO pin numbers as well as the BoosterPack compliant features can be viewed in the
. Each GPIO has multiple functions available through the F28003x device's
GPIO mux. Some specific functions have been listed in the Pinout Map; the full GPIO mux table can be found in
the
TMS320F28003x Real-Time Microcontrollers Data Sheet
All of the analog signals (denoted ADCIN) of the F28003x MCU are routed to the J1/J3 and J5/J7 BoosterPack
headers on the left side of the board. Close to the respective BoosterPack header each ADC input signal has
component pads for a series resistor and parallel capacitor to create an RC filter. By default a 0 ohm resistor
is populated and the capacitor is left un-populated. Users may wish to populate these components with specific
values in order to filter out noise arriving at the device's ADC input.
3.1.10 Analog Voltage Reference Header
The analog subsystem of the F28003x allows for flexible voltage reference sources. The ADC modules are
referenced to the VREFHIx and VREFLOx pin voltages. VREFHIx can either be driven externally or can be
generated by an internal bandgap voltage reference. An external voltage can be supplied to header J15 as an
external voltage source for VREFHIx. Note that there is no signal conditioning circuitry in place for the voltage
reference. For best performance, some additional circuitry may be required.
3.1.11 Other Headers and Jumpers
The LaunchPad has multiple jumpers to select different power sources for the board. This LaunchPad also
provides a way to isolate the connected USB from the device, allowing for safe operation and debugging in
higher voltage applications.
3.1.11.1 USB Isolation Block
JP1 is provided to enable isolation between the device and the connected USB in higher-voltage applications.
The area of isolation is defined by the white outline in the upper-left corner of the LaunchPad. JP1 has two
removable shunts to separate the GND and 5 V power of the USB region and the XDS110 and F28003x MCU
region of the LaunchPad. By default, both shunts are populated and the power is supplied by the connected
USB, meaning that the USB is NOT isolated from the XDS110 and F28003x MCU regions. If power isolation is
desired, remove the supplied shunts from JP1. In this configuration, one of the two external power options below
are required:
• An external 5 V supply to power the 3.3 V LDO (TPS7A3701), which provides 3.3 V to the XDS110 and
F28003x MCU regions of the board.
• An external 3.3 V supply to power the XDS110 and F28003x MCU regions of the board.
Some applications may not require 5 V to be supplied to the MCU region. In an isolated power application with
JP1 shunts removed, supplying 5 V to the XDS110 and F28003x MCU regions is optional.
3.1.11.2 BoosterPack Site 2 Power Isolation
JP8 is included to isolate 3.3 V and 5 V from the BoosterPack site 2 headers. This might be required if two
BoosterPacks are simultaneously connected to the LaunchPad and both provide power to the LaunchPad. If this
is the case, power can be isolated by removing the shunts on JP8 and there will be no contention between the
two BoosterPacks.
Hardware Description
SPRUJ31 – APRIL 2022
C2000
™
F28003x Series LaunchPad
™
Development Kit
13
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