Overview
13
SBOU103A – April 2011 – Revised May 2016
Copyright © 2011–2016, Texas Instruments Incorporated
BUF18830EVM User Guide and Software Tutorial
1.8
BUF18830EVM Features
This section describes some of the hardware features present on the BUF18830EVM test board.
JMP1: V
COM
Supply Control Setting
Jumper JMP1 selects where the BUF18830 V
COM
supply pin is connected. If JMP1 is set to the SHORT
position, the V
COM
supply pin is connected to the AV
DD
pin.
When JMP1 is set in the OPEN position, an external supply connected to terminal T6 can be used to
provide the V
COM
supply voltage for the BUF18830.
JMP2: I
2
C Address Hardware Setting
Jumper JMP2 is used to set the hardware setting for the A0 I
2
C address pin on the BUF18830. Using
JMP2, the A0 address can be set to either a logic '1' or a logic '0' to allow for two unique I
2
C addresses.
See
on how to configure the BUF18830EVM software to match the JMP2 hardware setting.
JMP3: DV
DD
Control Setting
Jumper JMP3 selects where the BUF18830 digital supply pin is connected. If JMP3 is set in the INT
position, the DV
D
D pin is connected to the switchable V
DU
T signal generated from the USB_DIG_Platform.
This voltage can be set to 3.3V or +5V depending on how JUMP9 on the USB_DIG_Platform is
set. While JMP3 is set to the INT position, the
DV
DD
Power
button on the BUF18830 software is able to
control whether the V
DUT
supply voltage is turned on or off.
When JMP3 is set in the EXT position, an external supply connected to terminal T1 can be used to
provide the digital supply voltage for the BUF18830.
BUF18830 Device Placement
The BUF18830EVM allows the user two separate locations on the board where the BUF18830 test device
can be installed.
The U1 location on the BUF18830 test board is a 38-pin QFN test socket that allows the user to evaluate
and program many devices very quickly. One drawback to this socket is that there are no connections to
the BUF18830 PowerPAD™. Because of this drawback, while in this socket, the BUF18830 cannot
operate at its full output capability as a result of thermal dissipation limitations.
The U2 location allows for a BUF18830 device that is soldered down on a DIP adapter board to be
installed on the BUF18830 test board. The output capability of the BUF18830 that is soldered on this
adapter board can be fully evaluated. The PowerPAD of this soldered BUF18830 unit is connected
correctly, and allows the device to dissipate the necessary power while being evaluated.
CAUTION
Only one location should be populated at a time. The use of both locations
simultaneously will damage one or both of the devices being tested.
Terminal Strip TPG1
Terminal strip TPG1 provides the individual output signals on a single row of headers as well as a row of
vias. This footprint provides the user with multiple options regarding how to interface the output signals of
the BUF18830 with the available display panel. Users can develop a custom cable to connect the headers
to their respective panels directly, or to solder directly to the individual vias.
