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1

Introduction

2

Considerations When Testing and Using bq24070 ICs

Introduction

The bq24070 powers the system while independently charging the battery. This feature reduces the
charge and discharge cycles on the battery, allows for proper charge termination, and allows the system
to run with an absent or defective battery pack. This feature also allows for the system to turn on
instantaneously from an external power source even when using a deeply discharged battery pack.

The IN pin can be programmed to perform like a USB input by pulling the MODE pin low or like an adapter
input if the MODE pin is pulled high. An external resistor, RSET1, sets the magnitude of the charge
current. If the charge current exceeds the available input current, the voltage on the OUT pin drops to the
DPPM

OUT

threshold or the battery voltage, whichever is higher. The charging current is reduced to what

current is available (I

BAT

= I

IN

– I

OUT

).

The bq24070 charges the battery in three phases: conditioning, constant current, and constant voltage.
Charge is terminated based on minimum current. A resistor-programmable charge timer provides a
backup safety for charge termination. The bq24070 automatically restarts the charge if the battery voltage
falls below an internal threshold. The bq24070 automatically enters sleep mode when both supplies are
removed (a drop to the battery voltage).

It is recommended to read the bq24070 data sheet prior to evaluating this EVM. Consider the following
noteworthy items while testing and using the bq24070 IC.

The two potential sources to power the system (V

OUT

) are: IN (adapter or USB source) and the battery.

The IC is designed to power the system continuously. The battery, in most cases, is the last line of
backup. If the adapter or USB input is not available (or disabled), the battery connects to the system.

In thermal regulation condition (T

J

= 125°C—not a first-choice design mode of operation), the charge

current is reduced to the battery, and the system still gets its power from the input. The battery
supplement is still available in thermal regulation if V

OUT

falls to V

BAT

. In thermal cutoff (~155°C), the input

sources are disconnected, but the internal battery FET connects the battery to V

OUT

.

There are two types of OUT-pin short circuit, one associated with the input IN pin (V

OUT

< 1 V) and the

other associated with the BAT pin (V

BAT

– V

OUT

> 200 mV). For the BAT short circuit, the battery FET

opens if a short on V

OUT

pulls more than ~4 A of current (>200-mV drop across the BAT FET) from the

battery. The recovery method is from a 10-mA current source between the BAT and OUT pins, so the
short and any system load must be removed before the OUT pin can recover within 200 mV of V

BAT

. Note

that the current source is ~10 mA with the OUT pin near 0 V, but falls off to ~2 mA as the OUT pin goes
above 1 V. For the IN-to-OUT short-circuit case where the OUT pin is less than 1 V, the recovery method
is by a 500-

pullup resistor from IN to OUT. The system load must be reduced (>200

) such that the

pullup can pull V

OUT

above 1 V.

When there is no power to the system and the battery is hot-plugged, the BAT-pin voltage leads the
OUT-pin voltage due to the system capacitance, and the output may go into BAT short-circuit mode. To
avoid this, a feature was added to the DPPM pin. If the voltage on the DPPM pin is held below 1 V, then
the short-circuit feature is disabled. Therefore, placing a small capacitor (~1 nF to 10 nF) across the
DPPM resistor delays the short-circuit protection on input power-up by a few microseconds.

Another feature that protects system integrity is dynamic power path management (DPPM). The voltage
on the DPPM pin (DPPM

IN

) times a scaling factor of ~1.15 is the DPPM

OUT

voltage. The DPPM

OUT

voltage

is the critical voltage, determined by the designer, where battery charging current is reduced to keep the
system voltage (V

OUT

) from further decay. A special feature to keep in mind is that when in DPPM mode,

the internal oscillator timer is slowed in proportion to the reduction in programmed charger current. This
allows the timers (safety and others) to be appropriately adjusted during operation. Therefore, when
performing any test where time is measured, keep in mind this adjustment factor.

The MODE (High/Low) sets which input source is present (adapter or USB). The CE pin (going high)
immediately enables the chip; disabling it (going low) delays handoff for 5 ms.

bq24070 1.5-A Single-Chip Li-Ion and Li-Pol Charge Management IC EVM

2

SLUU248 – May 2006

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Summary of Contents for bq24070

Page 1: ...er supply The charger is programmed from the factory to deliver 1 A of charging current Contents 1 Introduction 2 2 Considerations When Testing and Using bq24070 ICs 2 3 Performance Specification Summ...

Page 2: ...sconnected but the internal battery FET connects the battery to VOUT There are two types of OUT pin short circuit one associated with the input IN pin VOUT 1 V and the other associated with the BAT pi...

Page 3: ...1 W VBAT IBAT VIN VLDO ILDO 1 The HPA180 bq24070 thermal design is optimized 8 vias 0 031 inch PWB 2 oz copper to give JA 27 C W This section covers the setup and tests performed in evaluating the EVM...

Page 4: ...om the input 18 Disconnect the 5 25 VDC input supply from the UUT IN input Verify on the scope that VOUT does not drop out Verify VOUT is within 50 mV of VBAT and D2 STAT1 and D1 PG LEDs turn off This...

Page 5: ...at the charging terminates when the battery current tapers to C 10 or 100 mA 1 A 10 programmed charge current divided by 10 Verify D2 STAT1 turns off High and D3 STAT2 turns on Low 28 If a load is app...

Page 6: ...www ti com 5 Schematic S0200 01 Schematic Figure 2 bq24070 EVM Schematic bq24070 1 5 A Single Chip Li Ion and Li Pol Charge Management IC EVM 6 SLUU248 May 2006 Submit Documentation Feedback...

Page 7: ...op assembly view of the EVM Figure 5 shows the top etch layer of the EVM Figure 6 shows the board second etch layer of the EVM Figure 7 shows the board third etch layer of the EVM Figure 8 shows the b...

Page 8: ...30 1 79 K003 2 30 1 79 Physical Layouts Figure 4 Top Silkscreen Figure 5 Board Layout Top Etch Layer 8 bq24070 1 5 A Single Chip Li Ion and Li Pol Charge Management IC EVM SLUU248 May 2006 Submit Docu...

Page 9: ...005 2 30 1 79 Physical Layouts Figure 6 Board Layout Second Etch Layer Figure 7 Board Layout Third Etch Layer SLUU248 May 2006 bq24070 1 5 A Single Chip Li Ion and Li Pol Charge Management IC EVM 9 Su...

Page 10: ...ww ti com K006 2 30 1 79 Physical Layouts Figure 8 Board Layout Bottom Etch Layer bq24070 1 5 A Single Chip Li Ion and Li Pol Charge Management IC EVM 10 SLUU248 May 2006 Submit Documentation Feedback...

Page 11: ...6 1 1 k Resistor chip 1 k 1 10W 1 0805 Std Std R7 0 1 k Resistor chip 1 k 1 10W 1 0805 Std Std R9 1 10 k Resistor chip 10 k 1 16W 1 0603 Std Std R10 1 0 Resistor chip 0 1 16 W 1 0603 Std Std R11 1 22...

Page 12: ...y restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet...

Page 13: ...nd the output voltage range of 0 V to 6 5 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range p...

Page 14: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

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