Texas Instruments AN-2255, User Manual, Page: 14 / 26

PWM Dimming Control
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• Serial Interface Mode
• DC Interface Mode
The mode of PWM dimming control is selected by changing the position of the shunt jumper of J8.
Mode of dimming control Setting of J8
Direct PWM dimming mode Short Pos. 2–3
Serial interface mode Open
DC interface mode Short Pos. 1–2
Using PWM dimming control, the six output channels of the board are grouped into four individual groups
which are controlled by four individual PWM signals at the terminals TP12, TP14, TP16 and TP18.
Terminal Involved channels
TP12 CH0, CH1
TP14 CH2, CH3
TP16 CH4
TP18 CH5
The terminals J4, J5, J6 and J7 are used to connect the DIM01(TP12), DIM23(TP14), DIM4(TP16) and
DIM5(TP18) pins of the LM3463 to either VCC or GND. The jumpers on these terminals should be
removed if external dimming control signals are applied to the board.
Direct PWM Dimming Mode
In the direct PWM dimming mode, the board accepts standard active high TTL level PWM signals to
perform dimming control. The minimum on duty is generally limited by the gate capacitance of the external
MOSFETs. Normally, an 8 µs minimum on time is suggested.
Serial Interface Mode
In the serial interface mode, the on duty of each output channel is controlled by a data byte of 8 bits wide.
In this mode the terminals TP12, TP14 and TP16 on the board comprise a serial data interface to receive
data bytes from external data source. The connection to the DIM5 pin is not used and should be
connected to GND by shortening the pins 2 and 3 of J7. The functions of the TP12, TP14 and TP16 in the
serial interface mode are as listed in the following table:
Serial Interface Mode
Terminal Function
TP12 Serial data input
TP14 Clock signal input
TP16 End Of data Frame (EOF) signal input
In the serial interface mode the LM3463 evaluation board accepts a data frame which consists of four data
bytes to control the on duty of the four groups of output channels via the terminal TP12 (DIM01). Every
data byte contains 8 bits in LSB (Least Significant Bit) first ordering and is clocked into the data buffer of
the LM3463 at every rising edge of clock signal at the terminal TP14 (DIM23). Every time a data frame is
clocked in to the LM3463 the terminal TP16 (DIM4) should be pulled low to generate a falling edge to
indicate an ‘End-Of-Frame (EOF)’. Figure 7 shows the typical waveform of a data frame and the
corresponding clock and EOF signals.
14 AN-2255 LM3463 Evaluation Board SNVA642 – May 2012
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