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Application Information
•
After the data byte is sent, the master must check for another acknowledge to determine if the
LM49100 received the data.
•
If the master has more data bytes to send to the LM49100, then the master can repeat the previous
two steps until all data bytes have been sent.
•
The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal
is HIGH. The data line should be held HIGH when not in use.
Figure 19. I
2
C Bus Format
Figure 20. I
2
C Timing Diagram
15.5 I
2
C Interface Power Supply Pin (V
DD
I
2
C)
The LM49100's I
2
C interface is powered up through theV
DD
I
2
C pin. The LM49100's I
2
C interface operates
at a voltage level set by the V
DD
I
2
C pin which can be set independent to that of the main power supply pin
V
DD
. This is ideal whenever logic levels for the I
2
C interface are dictated by a microcontroller or
microprocessor that is operating at a lower supply voltage than the main battery of a portable system.
15
SNAA043A – October 2007 – Revised May 2013
AN-1622 LM49100 Evaluation Board»
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