Under/Overvoltage
Protection IC
TPS2400
6 V in
TPS7A4501
1.5-A Low Noise
Adjustable LDO
5 V
JP6
1 2
2-MHz, 500-mA
DC/DC Converter
TPS62237
500-mA Low Noise
Fixed Output LDO
TPS79533
500-mA Low Noise
Fixed Output LDO
TPS79518
JP7
3 4
1 2
6 V
2-MHz, 500-mA
DC/DC Converter
TPS62237
500-mA Low Noise
Fixed Output LDO
TPS79533
3.3 V
3.3 V
3.3 V
3.3 V
2-MHz, 500-mA
DC/DC Converter
TPS62237
1.8 V
1.8 V
1 2
JP9
3 4
1 2
JP12
3 4
JP8
1
2
3
1
2
3
1
2
3
JP10
JP11
3.3 V
AFE
3.3 V
CDC
1.8 V
AFE
Hardware Overview
1.4.5
Bypass CDCM7005
Bypassing the CDCM7005 entirely and simply supplying external clocks to the AFE7070 is possible. You
can use the SMA connector J12 to supply the LVPECL-level DACCLK signal if you install capacitors C129
and C130 and remove C102 and C103. A termination resistor may be placed at position R54, although
resistor R55 provides 100-
Ω
differential termination at the AFE7070’s DACCLK P and N inputs. When
setting the external clock’s amplitude, keep in mind the 2-to-1 impedance ratio of the transformer used for
single-ended-to-differential conversion.
Note that depending on the AFE7070’s clock mode, you may need to be send separate clock signals to
CLKIO or to the digital source as well. The SMA connector J11 can supply CLKIO, providing that you
install resistor R25 and remove R18. Connecting the TSW1400 CMOS clock input to an external clock
source is possible as well. Ensure that these various clock signals are synchronized and do not drift with
respect to one another.
1.5
Power Supply Options
The EVM provides multiple options for powering the AFE7070 and CDCM7005 integrated circuits (IC). By
default, users can power the board with a 6-Vdc adapter. Switched-mode dc/dc (buck) converters step
down this voltage to the necessary 3.3-V and 1.8-V rail voltages. If desired, users can use LDOs or bench
supplies rather than switching power supplies.
provides a simplified block diagram of the EVM’s
power architecture showing how jumper settings can be used to enable and disable various power supply
ICs. Also, disconnecting all jumpers and providing the necessary rail voltages directly to test points TP7,
TP6, and TP8 is possible.
Figure 2. EVM Power Architecture
For a detailed illustration of the EVM’s power supplies, see the circuit schematic included in the
Design
Files
on the
and
tool pages.
4
AFE707xEVM Evaluation Module
SLOU337A – March 2012 – Revised July 2015
Copyright © 2012–2015, Texas Instruments Incorporated
