Hardware Overview
1.3.3
RF Out
The AFE7070’s RF output (pin RFOUT) is ac-coupled by a 100 pF capacitor to the SMA connector J3.
This output can be connected directly to a 50-
Ω
spectrum analyzer or other test equipment.
1.3.4
LVDS Output
In the EVM’s default configuration, the AFE7070’s LVDS_P and LVDS_N outputs are routed directly to
SMA connectors J1 and J2, respectively. If desired, onboard termination can be added by populating
resistor R53; otherwise, properly terminate the signal with 100-
Ω
differential impedance at its sink.
The complementary LVDS outputs also can be converted to a single-ended signal for ease of
measurement. To do this, remove resistors R17 and R50, and place 0-
Ω
resistors at R21 and R38. This
routes the LVDS outputs to transformer T6 (connected to SMA connector J14) and disconnects them from
connectors J1 and J2. Place a resistor at position R53 to make the differential impedance
seen
by the
LVDS outputs equal to 100
Ω
. If the SMA connector J14 is connected to 50-
Ω
test equipment, the value of
R53 must be 200
Ω
, because the 50-
Ω
impedance is transformed to 200
Ω
on the primary side due to
transformer T6’s 4-to-1 impedance ratio.
The AFE7071 does not have this function.
1.4
Clocking Options
This EVM accommodates a wide range of clocking options. The AFE7070 has four clocking modes: Dual
Input Clock, Dual Output Clock, Single Differential DDR Clock, and Single Differential SDR Clock. See the
device data sheet for a detailed description of these four modes. The clock signals on the EVM can be
generated with the CDCM7005 or supplied externally. Similarly, the reference and VCXO inputs to the
CDCM7005 can come from onboard oscillators or other sources.
1.4.1
Default Configuration
By default, the CDCM7005 is configured to use an onboard 10-MHz reference and external VCXO input
signal to generate the AFE7070’s DACCLK and CLKIO signals. This is suitable for evaluating the
AFE7070’s Dual Input Clock, Single Differential DDR, and Single Differential SDR modes. A third
CDCM7005 output is routed to SMA connector J5. This signal can be sent to the TSW1400’s CMOS clock
input to align and synchronize the input data bus. Note that external equipment may be needed to add a
delay to this clock signal such that proper setup and hold times are maintained.
1.4.2
Dual Output Clock Mode
In Dual Output Clock mode, the AFE7070’s CLKIO pin becomes an output that can be used to drive a
digital source such as the TSW1400. To use this mode, the user must remove resistor R18 connecting
CLKIO to the CDCM7005’s output and instead populate resistor R25. This routes the CLKIO signal to
SMA connector J11. This output then can be connected to the TSW1400 CMOS clock input.
1.4.3
Onboard VCXO
If desired, a VCXO can be installed on the board at position VCXO1 to provide an input clock source to
the CDCM7005. In addition to populating the VCXO, remove resistor R13 and populate C29 with a 0-
Ω
resistor. This allows for dc-coupling a differential LVPECL-output VCXO (such as the TCO-2111) to the
VCXO_IN and VCXO_INB inputs of the CDCM7005.
1.4.4
External Reference Clock
The CDCM7005’s reference clock can be supplied externally as well. Because the CDCM7005 has two
reference inputs (primary and secondary), it is possible to simply connect an external CMOS-level clock to
SMA connector J6. The applied signal is ac-coupled and rebiased to a dc common-mode voltage of 1.65
V (midsupply), then applied to the CDCM7005’s PRI_REF input. If required, add a termination resistor to
position R26. Depending on the software settings, the CDCM7005 may automatically switch to the
external clock signal (automatic mode), or require the use of jumper JP3 to select it (manual mode).
3
SLOU337A – March 2012 – Revised July 2015
AFE707xEVM Evaluation Module
Copyright © 2012–2015, Texas Instruments Incorporated
