SDI
SCLK
SDO
CONVST
JP2
1
2
3
JP3
(CLOSED)
DVDD
10k
/CS
CONVST
J2:1 or J2:7
J2:17
ADS8860
/CS
CONVST
SDI
SCLK
SDO
CONVST
JP2
2
3
JP3
(OPEN)
DVDD
10k
/CS
/CS
J2:1 or J2:7
J2:17
ADS8860
EVM Digital Configuration
6
EVM Digital Configuration
The EVM offers two jumpers (JP2 and JP3) to configure the EVM in either 3-wire SPI mode or 4-wire SPI
mode. By default, the EVM jumper settings are 3-wire. JP1 only establishes the pin that carries the chip-
select signal from the J2 header.
6.1
SPI 3-Wire Mode (JP2:2–3 and JP3:OPEN)
The chip-select signal is used to bring the ADS8860 digital output out of 3-state and initializes
conversions. The rising edge of the chip-select signal starts a conversion, then after the conversion time,
the falling edge of the chip-select signal brings the digital output out of 3-state.
shows the serial
configuration for this mode.
Figure 4. Serial 3-Wire Configuration
6.2
SPI 4-Wire Mode (JP2:1–2 and JP3:CLOSED)
The chip-select signal is used to bring the ADS8860 digital output out of 3-state. However, conversion is
initialized from J3:17 as an independent signal. The rising edge of J3:17 (CONVST) starts a conversion,
then after the conversion time, the falling edge of the chip-select signal brings the digital output out of 3-
state.
shows the serial configuration for this mode.
Figure 5. Serial 4-Wire Configuration
8
ADS8860EVM-PDK
SBAU213 – September 2013
Copyright © 2013, Texas Instruments Incorporated
