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SBAS492 – JULY 2015
8.5.2.3.4.2
Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
There are two alarm thresholds (high and low) per channel, with two flags for each threshold. An active alarm
flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long
as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but
remains latched until read. Registers 11h to 14h in the program registers store the active and tripped alarm flags
for all individual eight channels.
Figure 114. ALARM Ch0-3 Tripped-Flag Register (address = 11h)
7
6
5
4
3
2
1
0
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Flag Ch0 Low
Flag Ch0 High
Flag Ch1 Low
Flag Ch1 High
Flag Ch2 Low
Flag Ch2 High
Flag Ch3 Low
Flag Ch3 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 17. ALARM Ch0-3 Tripped-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Tripped Alarm Flag Ch n
R
0h
Tripped alarm flag high, low for channel n (n = 0 to 3)
Low or High (n = 0 to 3)
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
Figure 115. ALARM Ch0-3 Active-Flag Register (address = 12h)
7
6
5
4
3
2
1
0
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Flag Ch0 Low
Flag Ch0 High
Flag Ch1 Low
Flag Ch1 High
Flag Ch2 Low
Flag Ch2 High
Flag Ch3 Low
Flag Ch3 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 18. ALARM Ch0-3 Active-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Active Alarm Flag Ch n Low
R
0h
Active alarm flag high, low for channel n (n = 0 to 3)
or High (n = 0 to 3)
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
Figure 116. ALARM Ch4-7 Tripped-Flag Register (address = 13h)
(1)
7
6
5
4
3
2
1
0
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Flag Ch4 Low
Flag Ch4 High
Flag Ch5 Low
Flag Ch5 High
Flag Ch6 Low
Flag Ch6 High
Flag Ch7 Low
Flag Ch7 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
(1)
This register is not included in the 4-channel version of the device. A write operation on this register has no effect on device behavior. A
read operation on this register outputs all 1's on the SDO line.
Table 19. ALARM Ch4-7 Tripped-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Tripped Alarm Flag Ch n
R
0h
Tripped alarm flag high, low for channel n (n = 4 to 7).
Low or High (n = 4 to 7)
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
Copyright © 2015, Texas Instruments Incorporated
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