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1
2
15
16
SCLK
CS
SDO
ADDR [6:0]
RD
X X X X X X
SDI
9
10
6
7
8
DOUT [7:0]
23
24
17
18
SBAS492 – JULY 2015
For a read cycle, the next eight bits (bits 7-0) on SDI are
don’t care
bits and SDO stays low. From the 16th SCLK
falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in
MSB-first fashion. A typical timing diagram for a program register read cycle is shown in
.
Table 8. Read Cycle Command Word
REGISTER ADDRESS
WR/RD
DATA
PIN
(Bits 15-9)
(Bit 8)
(Bits 7-0)
SDI
ADDR[6:0]
0
XXXXX
SDO
0000 000
0
DOUT[7:0]
Figure 108. Program Register Read Cycle Timing Diagram
Copyright © 2015, Texas Instruments Incorporated
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